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Searched refs:pe (Results 1 – 25 of 42) sorted by relevance

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/arch/powerpc/kernel/
Deeh_pe.c48 struct eeh_pe *pe; in eeh_pe_alloc() local
58 pe = kzalloc(alloc_size, GFP_KERNEL); in eeh_pe_alloc()
59 if (!pe) return NULL; in eeh_pe_alloc()
62 pe->type = type; in eeh_pe_alloc()
63 pe->phb = phb; in eeh_pe_alloc()
64 INIT_LIST_HEAD(&pe->child_list); in eeh_pe_alloc()
65 INIT_LIST_HEAD(&pe->edevs); in eeh_pe_alloc()
67 pe->data = (void *)pe + ALIGN(sizeof(struct eeh_pe), in eeh_pe_alloc()
69 return pe; in eeh_pe_alloc()
81 struct eeh_pe *pe; in eeh_phb_pe_create() local
[all …]
Deeh_driver.c106 if (eeh_pe_passed(edev->pe)) in eeh_edev_actionable()
223 if (edev->pe && (edev->pe->state & EEH_PE_CFG_RESTRICTED)) in eeh_dev_save_state()
235 struct eeh_pe *pe; in eeh_set_channel_state() local
238 eeh_for_each_pe(root, pe) in eeh_set_channel_state()
239 eeh_pe_for_each_dev(pe, edev, tmp) in eeh_set_channel_state()
246 struct eeh_pe *pe; in eeh_set_irq_state() local
249 eeh_for_each_pe(root, pe) { in eeh_set_irq_state()
250 eeh_pe_for_each_dev(pe, edev, tmp) { in eeh_set_irq_state()
309 !eeh_dev_removed(edev), !eeh_pe_passed(edev->pe)); in eeh_pe_report_edev()
320 struct eeh_pe *pe; in eeh_pe_report() local
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Deeh_event.c61 if (event->pe) in eeh_event_handler()
62 eeh_handle_normal_event(event->pe); in eeh_event_handler()
102 int __eeh_send_failure_event(struct eeh_pe *pe) in __eeh_send_failure_event() argument
112 event->pe = pe; in __eeh_send_failure_event()
119 if (pe) { in __eeh_send_failure_event()
125 pe->trace_entries = stack_trace_save(pe->stack_trace, in __eeh_send_failure_event()
126 ARRAY_SIZE(pe->stack_trace), 0); in __eeh_send_failure_event()
129 eeh_pe_state_mark(pe, EEH_PE_RECOVERING); in __eeh_send_failure_event()
143 int eeh_send_failure_event(struct eeh_pe *pe) in eeh_send_failure_event() argument
154 return __eeh_send_failure_event(pe); in eeh_send_failure_event()
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Deeh.c275 static void *eeh_dump_pe_log(struct eeh_pe *pe, void *flag) in eeh_dump_pe_log() argument
280 eeh_pe_for_each_dev(pe, edev, tmp) in eeh_dump_pe_log()
297 void eeh_slot_error_detail(struct eeh_pe *pe, int severity) in eeh_slot_error_detail() argument
317 if (!(pe->type & EEH_PE_PHB)) { in eeh_slot_error_detail()
320 eeh_pci_enable(pe, EEH_OPT_THAW_MMIO); in eeh_slot_error_detail()
334 eeh_ops->configure_bridge(pe); in eeh_slot_error_detail()
335 if (!(pe->state & EEH_PE_CFG_BLOCKED)) { in eeh_slot_error_detail()
336 eeh_pe_restore_bars(pe); in eeh_slot_error_detail()
339 eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen); in eeh_slot_error_detail()
343 eeh_ops->get_log(pe, severity, pci_regs_buf, loglen); in eeh_slot_error_detail()
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Deeh_sysfs.c63 if (!edev || !edev->pe) in eeh_pe_state_show()
66 state = eeh_ops->get_state(edev->pe, NULL); in eeh_pe_state_show()
68 state, edev->pe->state); in eeh_pe_state_show()
78 if (!edev || !edev->pe) in eeh_pe_state_store()
82 if (!(edev->pe->state & EEH_PE_ISOLATED)) in eeh_pe_state_store()
85 if (eeh_unfreeze_pe(edev->pe)) in eeh_pe_state_store()
87 eeh_pe_state_clear(edev->pe, EEH_PE_ISOLATED, true); in eeh_pe_state_store()
102 if (!edev || !edev->pe) in eeh_notify_resume_show()
116 if (!edev || !edev->pe || !eeh_ops->notify_resume) in eeh_notify_resume_store()
Drtas_pci.c56 if (pdn->edev && pdn->edev->pe && in rtas_read_config()
57 (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED)) in rtas_read_config()
107 if (pdn->edev && pdn->edev->pe && in rtas_write_config()
108 (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED)) in rtas_write_config()
Deeh_cache.c181 if (!edev->pe) { in __eeh_addr_cache_insert_dev()
/arch/powerpc/platforms/powernv/
Dpci-ioda.c53 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
55 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, in pe_level_printk() argument
67 if (pe->flags & PNV_IODA_PE_DEV) in pe_level_printk()
68 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); in pe_level_printk()
69 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) in pe_level_printk()
71 pci_domain_nr(pe->pbus), pe->pbus->number); in pe_level_printk()
73 else if (pe->flags & PNV_IODA_PE_VF) in pe_level_printk()
75 pci_domain_nr(pe->parent_dev->bus), in pe_level_printk()
76 (pe->rid & 0xff00) >> 8, in pe_level_printk()
77 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); in pe_level_printk()
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Dnpu-dma.c103 struct pnv_ioda_pe *pe; in get_gpu_pci_dev_and_pe() local
116 pe = &phb->ioda.pe_array[pdn->pe_number]; in get_gpu_pci_dev_and_pe()
121 return pe; in get_gpu_pci_dev_and_pe()
264 struct pnv_ioda_pe *pe[NV_NPU_MAX_PE_NUM]; member
282 if (!npucomp->pe_num || !npucomp->pe[0] || in pnv_npu_peers_create_table_userspace()
283 !npucomp->pe[0]->table_group.ops || in pnv_npu_peers_create_table_userspace()
284 !npucomp->pe[0]->table_group.ops->create_table) in pnv_npu_peers_create_table_userspace()
287 return npucomp->pe[0]->table_group.ops->create_table( in pnv_npu_peers_create_table_userspace()
288 &npucomp->pe[0]->table_group, num, page_shift, in pnv_npu_peers_create_table_userspace()
301 struct pnv_ioda_pe *pe = npucomp->pe[i]; in pnv_npu_peers_set_window() local
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Deeh-powernv.c124 struct eeh_pe *pe; in pnv_eeh_ei_write() local
145 pe = eeh_pe_get(hose, pe_no, 0); in pnv_eeh_ei_write()
146 if (!pe) in pnv_eeh_ei_write()
150 ret = eeh_ops->err_inject(pe, type, func, addr, mask); in pnv_eeh_ei_write()
380 if (!edev || edev->pe) in pnv_eeh_probe()
444 edev->pe->state |= EEH_PE_CFG_RESTRICTED; in pnv_eeh_probe()
452 if (!(edev->pe->state & EEH_PE_PRI_BUS)) { in pnv_eeh_probe()
453 edev->pe->bus = pci_find_bus(hose->global_number, in pnv_eeh_probe()
455 if (edev->pe->bus) in pnv_eeh_probe()
456 edev->pe->state |= EEH_PE_PRI_BUS; in pnv_eeh_probe()
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Dpci-cxl.c16 struct pnv_ioda_pe *pe; in pnv_phb_to_cxl_mode() local
19 pe = pnv_ioda_get_pe(dev); in pnv_phb_to_cxl_mode()
20 if (!pe) in pnv_phb_to_cxl_mode()
23 pe_info(pe, "Switching PHB to CXL\n"); in pnv_phb_to_cxl_mode()
25 rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); in pnv_phb_to_cxl_mode()
134 struct pnv_ioda_pe *pe; in pnv_cxl_ioda_msi_setup() local
137 if (!(pe = pnv_ioda_get_pe(dev))) in pnv_cxl_ioda_msi_setup()
141 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); in pnv_cxl_ioda_msi_setup()
143 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " in pnv_cxl_ioda_msi_setup()
Dpci.h203 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
205 #define pe_err(pe, fmt, ...) \ argument
206 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
207 #define pe_warn(pe, fmt, ...) \ argument
208 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
209 #define pe_info(pe, fmt, ...) \ argument
210 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
217 struct pnv_ioda_pe *pe);
219 struct pnv_ioda_pe *pe);
Dpci.c725 if (edev->pe && in pnv_pci_cfg_check()
726 (edev->pe->state & EEH_PE_CFG_BLOCKED)) in pnv_pci_cfg_check()
818 struct pnv_ioda_pe *pe; in pnv_pci_dma_dev_setup() local
825 list_for_each_entry(pe, &phb->ioda.pe_list, list) { in pnv_pci_dma_dev_setup()
826 if (pe->rid == ((pdev->bus->number << 8) | in pnv_pci_dma_dev_setup()
828 pdn->pe_number = pe->pe_number; in pnv_pci_dma_dev_setup()
829 pe->pdev = pdev; in pnv_pci_dma_dev_setup()
844 struct pnv_ioda_pe *pe; in pnv_pci_dma_bus_setup() local
846 list_for_each_entry(pe, &phb->ioda.pe_list, list) { in pnv_pci_dma_bus_setup()
847 if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))) in pnv_pci_dma_bus_setup()
[all …]
/arch/alpha/include/asm/
Dcore_marvel.h57 #define EV7_IPE(pe) ((~((long)(pe)) & EV7_PE_MASK) << 35) argument
59 #define EV7_CSR_PHYS(pe, off) (EV7_IPE(pe) | (0x7FFCUL << 20) | (off)) argument
60 #define EV7_CSRS_PHYS(pe) (EV7_CSR_PHYS(pe, 0UL)) argument
62 #define EV7_CSR_KERN(pe, off) (EV7_KERN_ADDR(EV7_CSR_PHYS(pe, off))) argument
63 #define EV7_CSRS_KERN(pe) (EV7_KERN_ADDR(EV7_CSRS_PHYS(pe))) argument
249 #define IO7_IPE(pe) (EV7_IPE(pe)) argument
252 #define IO7_HOSE(pe, port) (IO7_IPE(pe) | IO7_IPORT(port)) argument
254 #define IO7_MEM_PHYS(pe, port) (IO7_HOSE(pe, port) | 0x00000000UL) argument
255 #define IO7_CONF_PHYS(pe, port) (IO7_HOSE(pe, port) | 0xFE000000UL) argument
256 #define IO7_IO_PHYS(pe, port) (IO7_HOSE(pe, port) | 0xFF000000UL) argument
[all …]
/arch/powerpc/platforms/pseries/
Deeh_pseries.c236 struct eeh_pe pe; in pseries_eeh_probe() local
243 if (!edev || edev->pe) in pseries_eeh_probe()
280 memset(&pe, 0, sizeof(struct eeh_pe)); in pseries_eeh_probe()
281 pe.phb = pdn->phb; in pseries_eeh_probe()
282 pe.config_addr = (pdn->busno << 16) | (pdn->devfn << 8); in pseries_eeh_probe()
286 ret = eeh_ops->set_option(&pe, EEH_OPT_ENABLE); in pseries_eeh_probe()
291 edev->pe_config_addr = eeh_ops->get_pe_addr(&pe); in pseries_eeh_probe()
292 pe.addr = edev->pe_config_addr; in pseries_eeh_probe()
298 ret = eeh_ops->get_state(&pe, NULL); in pseries_eeh_probe()
306 (pdn_to_eeh_dev(pdn->parent))->pe) { in pseries_eeh_probe()
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Dmsi.c200 if (edev->pe) in find_pe_dn()
201 edev = list_first_entry(&edev->pe->edevs, struct eeh_dev, in find_pe_dn()
/arch/powerpc/include/asm/
Deeh.h106 #define eeh_pe_for_each_dev(pe, edev, tmp) \ argument
107 list_for_each_entry_safe(edev, tmp, &pe->edevs, entry)
109 #define eeh_for_each_pe(root, pe) \ argument
110 for (pe = root; pe; pe = eeh_pe_next(pe, root))
112 static inline bool eeh_pe_passed(struct eeh_pe *pe) in eeh_pe_passed() argument
114 return pe ? !!atomic_read(&pe->pass_dev_cnt) : false; in eeh_pe_passed()
145 struct eeh_pe *pe; /* Associated PE */ member
159 ((edev)->pe ? (edev)->pe_config_addr : 0xffff), ##__VA_ARGS__)
177 return edev ? edev->pe : NULL; in eeh_dev_to_pe()
219 int (*set_option)(struct eeh_pe *pe, int option);
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Deeh_event.h19 struct eeh_pe *pe; /* EEH PE */ member
23 int eeh_send_failure_event(struct eeh_pe *pe);
24 int __eeh_send_failure_event(struct eeh_pe *pe);
25 void eeh_remove_event(struct eeh_pe *pe, bool force);
26 void eeh_handle_normal_event(struct eeh_pe *pe);
Dppc-pci.h50 void eeh_slot_error_detail(struct eeh_pe *pe, int severity);
51 int eeh_pci_enable(struct eeh_pe *pe, int function);
52 int eeh_pe_reset_full(struct eeh_pe *pe, bool include_passed);
56 void eeh_pe_state_mark(struct eeh_pe *pe, int state);
57 void eeh_pe_mark_isolated(struct eeh_pe *pe);
58 void eeh_pe_state_clear(struct eeh_pe *pe, int state, bool include_passed);
59 void eeh_pe_state_mark_with_cfg(struct eeh_pe *pe, int state);
60 void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode);
/arch/alpha/kernel/
Dcore_marvel.c56 read_ev7_csr(int pe, unsigned long offset) in read_ev7_csr() argument
58 ev7_csr *ev7csr = EV7_CSR_KERN(pe, offset); in read_ev7_csr()
69 write_ev7_csr(int pe, unsigned long offset, unsigned long q) in write_ev7_csr() argument
71 ev7_csr *ev7csr = EV7_CSR_KERN(pe, offset); in write_ev7_csr()
79 mk_resource_name(int pe, int port, char *str) in mk_resource_name() argument
84 sprintf(tmp, "PCI %s PE %d PORT %d", str, pe, port); in mk_resource_name()
101 marvel_find_io7(int pe) in marvel_find_io7() argument
105 for (io7 = io7_head; io7 && io7->pe != pe; io7 = io7->next) in marvel_find_io7()
112 alloc_io7(unsigned int pe) in alloc_io7() argument
118 if (marvel_find_io7(pe)) { in alloc_io7()
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Dperf_event.c344 struct perf_event *pe; in collect_events() local
354 for_each_sibling_event(pe, group) { in collect_events()
355 if (!is_software_event(pe) && pe->state != PERF_EVENT_STATE_OFF) { in collect_events()
358 event[n] = pe; in collect_events()
359 evtype[n] = pe->hw.event_base; in collect_events()
400 struct perf_event *pe = cpuc->event[j]; in maybe_change_configuration() local
403 cpuc->current_idx[j] != pe->hw.idx) { in maybe_change_configuration()
404 alpha_perf_event_update(pe, &pe->hw, cpuc->current_idx[j], 0); in maybe_change_configuration()
412 struct perf_event *pe = cpuc->event[j]; in maybe_change_configuration() local
413 struct hw_perf_event *hwc = &pe->hw; in maybe_change_configuration()
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Dsys_marvel.c250 long base = (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT) + 16; in init_io7_irqs()
254 io7->pe, base); in init_io7_irqs()
360 (irq + 16) | (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT), in marvel_map_irq()
361 (irq + 16) | (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT)); in marvel_map_irq()
375 irq |= io7->pe << MARVEL_IRQ_VEC_PE_SHIFT; /* merge the pid */ in marvel_map_irq()
Dproto.h59 struct io7 *marvel_find_io7(int pe);
/arch/arm/boot/dts/
Dsuniv-f1c100s.dtsi92 uart0_pe_pins: uart0-pe-pins {
Dsun9i-a80-cubieboard4.dts198 vcc-pe-supply = <&reg_eldo2>;
315 regulator-name = "vcc-pe";

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