| /arch/mips/include/asm/mach-pmcs-msp71xx/ |
| D | msp_prom.h | 27 #define FPGA_IS_POLO(revision) \ argument
28 (((revision >= 0xb0) && (revision < 0xd0)))
29 #define FPGA_IS_5000(revision) \ argument
30 ((revision >= 0x80) && (revision <= 0x90))
31 #define FPGA_IS_ZEUS(revision) ((revision < 0x7f)) argument
32 #define FPGA_IS_DUET(revision) \ argument
33 (((revision >= 0xa0) && (revision < 0xb0)))
34 #define FPGA_IS_MSP4200(revision) ((revision >= 0xd0)) argument
35 #define FPGA_IS_MSP7100(revision) ((revision >= 0xd0)) argument
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| /arch/arm/mach-zynq/ |
| D | common.c | 71 u32 revision; in zynq_get_revision() local
85 revision = readl(zynq_devcfg_base + ZYNQ_DEVCFG_MCTRL); in zynq_get_revision()
86 revision >>= ZYNQ_DEVCFG_PS_VERSION_SHIFT; in zynq_get_revision()
87 revision &= ZYNQ_DEVCFG_PS_VERSION_MASK; in zynq_get_revision()
91 return revision; in zynq_get_revision()
117 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "0x%x", system_rev); in zynq_init_machine()
124 kfree(soc_dev_attr->revision); in zynq_init_machine()
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| /arch/arm/mach-imx/ |
| D | mach-imx7ulp.c | 23 u32 revision; in imx7ulp_set_revision() local
31 if (regmap_read(sim, SIM_JTAG_ID_REG, &revision)) { in imx7ulp_set_revision()
41 switch (revision >> 28) { in imx7ulp_set_revision()
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| D | anatop.c | 113 unsigned int revision; in imx_init_revision_from_anatop() local
133 revision = digprog & 0xff; in imx_init_revision_from_anatop()
146 revision = ((major_part + 1) << 4) | minor_part; in imx_init_revision_from_anatop()
168 imx_set_soc_revision(revision); in imx_init_revision_from_anatop()
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| D | cpu.c | 156 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d", in imx_soc_device_init()
159 if (!soc_dev_attr->revision) in imx_soc_device_init()
169 kfree(soc_dev_attr->revision); in imx_soc_device_init()
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| /arch/mips/pci/ |
| D | fixup-cobalt.c | 103 printk(KERN_INFO "Galileo: revision %u\n", dev->revision); in qube_raq_galileo_fixup()
106 if (dev->revision >= 0x10) { in qube_raq_galileo_fixup()
109 } else if (dev->revision == 0x1 || dev->revision == 0x2) in qube_raq_galileo_fixup()
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| /arch/x86/include/asm/ |
| D | cpu_device_id.h | 30 #define INTEL_CPU_DESC(model, stepping, revision) { \ argument
35 .x86_microcode_rev = (revision), \
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| /arch/mips/pmcs-msp71xx/ |
| D | msp_setup.c | 150 unsigned long revision; in prom_init() local
164 revision = identify_revision(); in prom_init()
168 if (FPGA_IS_MSP4200(revision)) { in prom_init()
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| /arch/powerpc/platforms/52xx/ |
| D | efika.c | 145 const char *revision; in efika_show_cpuinfo() local
153 revision = of_get_property(root, "revision", NULL); in efika_show_cpuinfo()
162 if (revision) in efika_show_cpuinfo()
163 seq_printf(m, "revision\t: %s\n", revision); in efika_show_cpuinfo()
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| /arch/m68k/include/asm/ |
| D | dvma.h | 126 enum dvma_rev revision; member
132 #define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
133 #define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
234 if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
|
| /arch/arm64/kernel/ |
| D | acpi.c | 153 if (table->revision < 5 || in acpi_fadt_sanity_check()
154 (table->revision == 5 && fadt->minor_revision < 1)) { in acpi_fadt_sanity_check()
156 table->revision, fadt->minor_revision); in acpi_fadt_sanity_check()
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| /arch/arm/mach-omap1/ |
| D | gpio15xx.c | 41 .revision = USHRT_MAX,
82 .revision = USHRT_MAX,
|
| D | gpio7xx.c | 48 .revision = USHRT_MAX,
89 .revision = USHRT_MAX,
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| /arch/x86/xen/ |
| D | efi.c | 24 .revision = 0, /* Initialized later. */
73 efi_systab_xen.fw_revision = info->vendor.revision; in xen_efi_probe()
82 efi_systab_xen.hdr.revision = info->version; in xen_efi_probe()
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| /arch/arm/mach-omap2/ |
| D | dma.c | 115 u8 revision = dma_read(REVISION, 0) & 0xff; in omap2_show_dma_caps() local
117 revision >> 4, revision & 0xf); in omap2_show_dma_caps()
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| /arch/arm/mach-mvebu/ |
| D | mvebu-soc-id.c | 165 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X", soc_rev); in mvebu_soc_device()
171 kfree(soc_dev_attr->revision); in mvebu_soc_device()
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| /arch/alpha/include/asm/ |
| D | hwrpb.h | 99 unsigned long revision; member
167 unsigned long revision; member
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| /arch/x86/kernel/cpu/mce/ |
| D | apei.c | 77 rcd.hdr.revision = CPER_RECORD_REV; in apei_write_mce()
91 rcd.sec_hdr.revision = CPER_SEC_REV; in apei_write_mce()
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| /arch/arm/mm/ |
| D | cache-l2x0.c | 541 unsigned revision; in l2c310_save() local
554 revision = readl_relaxed(base + L2X0_CACHE_ID) & in l2c310_save()
558 if (revision >= L310_CACHE_ID_RTL_R2P0) in l2c310_save()
563 if (revision >= L310_CACHE_ID_RTL_R3P0) in l2c310_save()
570 unsigned revision; in l2c310_configure() local
584 revision = readl_relaxed(base + L2X0_CACHE_ID) & in l2c310_configure()
587 if (revision >= L310_CACHE_ID_RTL_R2P0) in l2c310_configure()
590 if (revision >= L310_CACHE_ID_RTL_R3P0) in l2c310_configure()
684 unsigned revision = cache_id & L2X0_CACHE_ID_RTL_MASK; in l2c310_fixup() local
689 revision < L310_CACHE_ID_RTL_R2P0 && in l2c310_fixup()
[all …]
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| /arch/ia64/include/asm/ |
| D | fpswa.h | 67 unsigned int revision; member
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| /arch/arm/boot/dts/ |
| D | armada-388-clearfog-pro.dts | 3 * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828)
|
| D | omap34xx.dtsi | 109 * revision register instead of the unreadable OCP revision
110 * register. Also note that on early 34xx es1 revision there
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| /arch/x86/pci/ |
| D | pcbios.c | 67 unsigned char revision; /* Revision level, 0 */ member
318 if (check->fields.revision != 0) { in pci_find_bios()
320 check->fields.revision, check); in pci_find_bios()
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| /arch/mips/kernel/ |
| D | mips-cm.c | 333 unsigned long revision; in mips_cm_error_report() local
340 revision = mips_cm_revision(); in mips_cm_error_report()
345 if (revision < CM_REV_CM3) { /* CM2 */ in mips_cm_error_report()
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| /arch/arm64/boot/dts/xilinx/ |
| D | zynqmp-zcu102-rev1.0.dts | 33 board_revision: board-revision@e0 {
|