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Searched refs:sequence (Results 1 – 25 of 30) sorted by relevance

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/arch/parisc/kernel/
Dperf_asm.S141 blr %r1,%r0 ; branch to 8-instruction sequence
149 ; RDR 0 sequence
161 ; RDR 1 sequence
173 ; RDR 2 read sequence
185 ; RDR 3 read sequence
197 ; RDR 4 read sequence
209 ; RDR 5 read sequence
221 ; RDR 6 read sequence
233 ; RDR 7 read sequence
245 ; RDR 8 read sequence
[all …]
/arch/s390/kernel/
Dlgr.c33 char sequence[16]; member
77 cpascii(lgr_info->sequence, si->sequence, sizeof(si->sequence)); in lgr_stsi_1_1_1()
Dsysinfo.c87 EBCASC(info->sequence, sizeof(info->sequence)); in stsi_1_1_1()
107 seq_printf(m, "Sequence Code: %-16.16s\n", info->sequence); in stsi_1_1_1()
Dsthyi.c196 memcpy(sctns->mac.infmseq, sysinfo->sequence, sizeof(sctns->mac.infmseq)); in fill_stsi_mac()
/arch/s390/include/asm/
Dsysinfo.h30 char sequence[16]; member
47 char sequence[16]; member
80 char sequence[16]; member
/arch/um/drivers/
Dvector_transports.c32 uint32_t sequence; member
100 uint32_t *sequence; in gre_form_header() local
105 sequence = (uint32_t *)(header + td->sequence_offset); in gre_form_header()
107 *sequence = 0; in gre_form_header()
109 *sequence = cpu_to_be32(++td->sequence); in gre_form_header()
252 td->sequence = 0; in build_gre_transport_data()
283 td->sequence = false; in build_gre_transport_data()
/arch/arc/include/asm/
Dtlb-mmu1.h22 ; and its unpleasant LFSR pseudo-random sequence
/arch/x86/include/asm/uv/
Duv_bau.h278 unsigned int sequence:16; /* message sequence number */ member
392 unsigned int sequence:16; /* message sequence number */ member
480 unsigned short sequence; /* message sequence number */ member
/arch/mips/kvm/
D00README.txt24 …Linux-3.7-rc2 based SMP guest hangs due to the following code sequence in the generated TLB handle…
/arch/mips/include/asm/octeon/
Dcvmx-lmcx-defs.h489 uint64_t sequence:3; member
509 uint64_t sequence:3;
538 uint64_t sequence:3; member
558 uint64_t sequence:3;
581 uint64_t sequence:3; member
601 uint64_t sequence:3;
625 uint64_t sequence:3; member
645 uint64_t sequence:3;
1146 uint64_t sequence:3; member
1156 uint64_t sequence:3;
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/arch/arm/mach-sa1100/
Dsleep.S47 @ avoid accessing memory until this sequence is complete,
/arch/x86/kernel/
Dtsc.c69 seq = this_cpu_read(cyc2ns.seq.sequence); in cyc2ns_read_begin()
76 } while (unlikely(seq != this_cpu_read(cyc2ns.seq.sequence))); in cyc2ns_read_begin()
/arch/arm64/
DKconfig333 This option adds an alternative code sequence to work around ARM
355 This option adds an alternative code sequence to work around ARM
377 This option adds an alternative code sequence to work around ARM
400 This option adds an alternative code sequence to work around ARM
404 If the processor is executing a load and store exclusive sequence at
421 This option adds an alternative code sequence to work around ARM
440 This option adds an alternative code sequence to work around ARM
461 This option adds an alternative code sequence to work around ARM
540 break-before-make sequence, then under very rare circumstances
632 Work around the issue by avoiding the problematic code sequence and
/arch/m68k/fpsp040/
Dbugfix.S341 | the code sequence to allow completion. We will jump to
478 | the code sequence to allow completion. fpsp_fmt_error causes
/arch/arm64/boot/dts/amlogic/
Dmeson-gxbb-odroidc2.dts155 * This signal should be handled by a USB specific power sequence
Dmeson-g12b-odroid-n2.dts370 * This signal should be handled by a USB specific power sequence
/arch/x86/kernel/acpi/
Dboot.c878 hpet_blockid = hpet_tbl->sequence; in acpi_parse_hpet()
928 hpet_tbl->sequence); in acpi_parse_hpet()
/arch/arm/boot/dts/
Dmeson8b-odroidc1.dts288 * This signal should be handled by a USB specific power sequence
Daspeed-bmc-opp-mihawk.dts744 /* FPGA for power sequence */
/arch/m68k/q40/
DREADME132 - exact keypress/release sequence
/arch/m68k/ifpsp060/
Dilsp.doc80 the 060ILSP entry table. A compiler generated code sequence
/arch/arm/kernel/
Dentry-header.S324 @ monitor is part of the exception entry and exit sequence.
/arch/arm/
DKconfig857 r1p* erratum. If a code sequence containing an ARM/Thumb
858 interworking branch is replaced with another code sequence at the
862 executing the new code sequence in the incorrect ARM or Thumb state.
1055 - Cortex-A12 852422: Execution of a sequence of instructions might
1060 sequence of 2 instructions that use opposing condition codes.
1063 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1067 (all revs) erratum. In very rare timing conditions, a sequence
1103 - Cortex-A17 852423: Execution of a sequence of instructions might
1642 memory write throughput than a sequence of individual 32bit stores.
/arch/x86/platform/uv/
Dtlb_uv.c943 uv1_hdr->sequence = seq_number; in uv_flush_send_and_wait()
945 uv2_3_hdr->sequence = seq_number; in uv_flush_send_and_wait()
/arch/x86/
DKconfig.cpu345 # Furthermore, AMD chips prefer a totally different sequence of NOPs

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