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1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * SGI UV Broadcast Assist Unit definitions
7  *
8  * Copyright (C) 2008-2011 Silicon Graphics, Inc. All rights reserved.
9  */
10 
11 #ifndef _ASM_X86_UV_UV_BAU_H
12 #define _ASM_X86_UV_UV_BAU_H
13 
14 #include <linux/bitmap.h>
15 #define BITSPERBYTE 8
16 
17 /*
18  * Broadcast Assist Unit messaging structures
19  *
20  * Selective Broadcast activations are induced by software action
21  * specifying a particular 8-descriptor "set" via a 6-bit index written
22  * to an MMR.
23  * Thus there are 64 unique 512-byte sets of SB descriptors - one set for
24  * each 6-bit index value. These descriptor sets are mapped in sequence
25  * starting with set 0 located at the address specified in the
26  * BAU_SB_DESCRIPTOR_BASE register, set 1 is located at BASE + 512,
27  * set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on.
28  *
29  * We will use one set for sending BAU messages from each of the
30  * cpu's on the uvhub.
31  *
32  * TLB shootdown will use the first of the 8 descriptors of each set.
33  * Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set).
34  */
35 
36 #define MAX_CPUS_PER_UVHUB		128
37 #define MAX_CPUS_PER_SOCKET		64
38 #define ADP_SZ				64 /* hardware-provided max. */
39 #define UV_CPUS_PER_AS			32 /* hardware-provided max. */
40 #define ITEMS_PER_DESC			8
41 /* the 'throttle' to prevent the hardware stay-busy bug */
42 #define MAX_BAU_CONCURRENT		3
43 #define UV_ACT_STATUS_MASK		0x3
44 #define UV_ACT_STATUS_SIZE		2
45 #define UV_DISTRIBUTION_SIZE		256
46 #define UV_SW_ACK_NPENDING		8
47 #define UV1_NET_ENDPOINT_INTD		0x38
48 #define UV2_NET_ENDPOINT_INTD		0x28
49 #define UV_NET_ENDPOINT_INTD		(is_uv1_hub() ?			\
50 			UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)
51 #define UV_PAYLOADQ_GNODE_SHIFT		49
52 #define UV_PTC_BASENAME			"sgi_uv/ptc_statistics"
53 #define UV_BAU_BASENAME			"sgi_uv/bau_tunables"
54 #define UV_BAU_TUNABLES_DIR		"sgi_uv"
55 #define UV_BAU_TUNABLES_FILE		"bau_tunables"
56 #define WHITESPACE			" \t\n"
57 #define cpubit_isset(cpu, bau_local_cpumask) \
58 	test_bit((cpu), (bau_local_cpumask).bits)
59 
60 /* [19:16] SOFT_ACK timeout period  19: 1 is urgency 7  17:16 1 is multiplier */
61 /*
62  * UV2: Bit 19 selects between
63  *  (0): 10 microsecond timebase and
64  *  (1): 80 microseconds
65  *  we're using 560us, similar to UV1: 65 units of 10us
66  */
67 #define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
68 #define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
69 
70 #define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD	(is_uv1_hub() ?			\
71 		UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD :			\
72 		UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)
73 /* assuming UV3 is the same */
74 
75 #define BAU_MISC_CONTROL_MULT_MASK	3
76 
77 #define UVH_AGING_PRESCALE_SEL		0x000000b000UL
78 /* [30:28] URGENCY_7  an index into a table of times */
79 #define BAU_URGENCY_7_SHIFT		28
80 #define BAU_URGENCY_7_MASK		7
81 
82 #define UVH_TRANSACTION_TIMEOUT		0x000000b200UL
83 /* [45:40] BAU - BAU transaction timeout select - a multiplier */
84 #define BAU_TRANS_SHIFT			40
85 #define BAU_TRANS_MASK			0x3f
86 
87 /*
88  * shorten some awkward names
89  */
90 #define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
91 #define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
92 #define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
93 #define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
94 #define PREFETCH_HINT_SHFT UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_SHFT
95 #define SB_STATUS_SHFT UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
96 #define write_gmmr	uv_write_global_mmr64
97 #define write_lmmr	uv_write_local_mmr
98 #define read_lmmr	uv_read_local_mmr
99 #define read_gmmr	uv_read_global_mmr64
100 
101 /*
102  * bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1
103  */
104 #define DS_IDLE				0
105 #define DS_ACTIVE			1
106 #define DS_DESTINATION_TIMEOUT		2
107 #define DS_SOURCE_TIMEOUT		3
108 /*
109  * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2
110  * values 1 and 3 will not occur
111  *        Decoded meaning              ERROR  BUSY    AUX ERR
112  * -------------------------------     ----   -----   -------
113  * IDLE                                 0       0        0
114  * BUSY (active)                        0       1        0
115  * SW Ack Timeout (destination)         1       0        0
116  * SW Ack INTD rejected (strong NACK)   1       0        1
117  * Source Side Time Out Detected        1       1        0
118  * Destination Side PUT Failed          1       1        1
119  */
120 #define UV2H_DESC_IDLE			0
121 #define UV2H_DESC_BUSY			2
122 #define UV2H_DESC_DEST_TIMEOUT		4
123 #define UV2H_DESC_DEST_STRONG_NACK	5
124 #define UV2H_DESC_SOURCE_TIMEOUT	6
125 #define UV2H_DESC_DEST_PUT_ERR		7
126 
127 /*
128  * delay for 'plugged' timeout retries, in microseconds
129  */
130 #define PLUGGED_DELAY			10
131 
132 /*
133  * threshholds at which to use IPI to free resources
134  */
135 /* after this # consecutive 'plugged' timeouts, use IPI to release resources */
136 #define PLUGSB4RESET			100
137 /* after this many consecutive timeouts, use IPI to release resources */
138 #define TIMEOUTSB4RESET			1
139 /* at this number uses of IPI to release resources, giveup the request */
140 #define IPI_RESET_LIMIT			1
141 /* after this # consecutive successes, bump up the throttle if it was lowered */
142 #define COMPLETE_THRESHOLD		5
143 /* after this # of giveups (fall back to kernel IPI's) disable the use of
144    the BAU for a period of time */
145 #define GIVEUP_LIMIT			100
146 
147 #define UV_LB_SUBNODEID			0x10
148 
149 /* these two are the same for UV1 and UV2: */
150 #define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
151 #define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
152 /* 4 bits of software ack period */
153 #define UV2_ACK_MASK			0x7UL
154 #define UV2_ACK_UNITS_SHFT		3
155 #define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
156 
157 /*
158  * number of entries in the destination side payload queue
159  */
160 #define DEST_Q_SIZE			20
161 /*
162  * number of destination side software ack resources
163  */
164 #define DEST_NUM_RESOURCES		8
165 /*
166  * completion statuses for sending a TLB flush message
167  */
168 #define FLUSH_RETRY_PLUGGED		1
169 #define FLUSH_RETRY_TIMEOUT		2
170 #define FLUSH_GIVEUP			3
171 #define FLUSH_COMPLETE			4
172 
173 /*
174  * tuning the action when the numalink network is extremely delayed
175  */
176 #define CONGESTED_RESPONSE_US		1000	/* 'long' response time, in
177 						   microseconds */
178 #define CONGESTED_REPS			10	/* long delays averaged over
179 						   this many broadcasts */
180 #define DISABLED_PERIOD			10	/* time for the bau to be
181 						   disabled, in seconds */
182 /* see msg_type: */
183 #define MSG_NOOP			0
184 #define MSG_REGULAR			1
185 #define MSG_RETRY			2
186 
187 #define BAU_DESC_QUALIFIER		0x534749
188 
189 enum uv_bau_version {
190 	UV_BAU_V1 = 1,
191 	UV_BAU_V2,
192 	UV_BAU_V3,
193 	UV_BAU_V4,
194 };
195 
196 /*
197  * Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
198  * If the 'multilevel' flag in the header portion of the descriptor
199  * has been set to 0, then endpoint multi-unicast mode is selected.
200  * The distribution specification (32 bytes) is interpreted as a 256-bit
201  * distribution vector. Adjacent bits correspond to consecutive even numbered
202  * nodeIDs. The result of adding the index of a given bit to the 15-bit
203  * 'base_dest_nasid' field of the header corresponds to the
204  * destination nodeID associated with that specified bit.
205  */
206 struct pnmask {
207 	unsigned long		bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
208 };
209 
210 /*
211  * mask of cpu's on a uvhub
212  * (during initialization we need to check that unsigned long has
213  *  enough bits for max. cpu's per uvhub)
214  */
215 struct bau_local_cpumask {
216 	unsigned long		bits;
217 };
218 
219 /*
220  * Payload: 16 bytes (128 bits) (bytes 0x20-0x2f of descriptor)
221  * only 12 bytes (96 bits) of the payload area are usable.
222  * An additional 3 bytes (bits 27:4) of the header address are carried
223  * to the next bytes of the destination payload queue.
224  * And an additional 2 bytes of the header Suppl_A field are also
225  * carried to the destination payload queue.
226  * But the first byte of the Suppl_A becomes bits 127:120 (the 16th byte)
227  * of the destination payload queue, which is written by the hardware
228  * with the s/w ack resource bit vector.
229  * [ effective message contents (16 bytes (128 bits) maximum), not counting
230  *   the s/w ack bit vector  ]
231  */
232 
233 /**
234  * struct uv1_2_3_bau_msg_payload - defines payload for INTD transactions
235  * @address:		Signifies a page or all TLB's of the cpu
236  * @sending_cpu:	CPU from which the message originates
237  * @acknowledge_count:	CPUs on the destination Hub that received the interrupt
238  */
239 struct uv1_2_3_bau_msg_payload {
240 	u64 address;
241 	u16 sending_cpu;
242 	u16 acknowledge_count;
243 };
244 
245 /**
246  * struct uv4_bau_msg_payload - defines payload for INTD transactions
247  * @address:		Signifies a page or all TLB's of the cpu
248  * @sending_cpu:	CPU from which the message originates
249  * @acknowledge_count:	CPUs on the destination Hub that received the interrupt
250  * @qualifier:		Set by source to verify origin of INTD broadcast
251  */
252 struct uv4_bau_msg_payload {
253 	u64 address;
254 	u16 sending_cpu;
255 	u16 acknowledge_count;
256 	u32 reserved:8;
257 	u32 qualifier:24;
258 };
259 
260 /*
261  * UV1 Message header:  16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
262  * see table 4.2.3.0.1 in broacast_assist spec.
263  */
264 struct uv1_bau_msg_header {
265 	unsigned int	dest_subnodeid:6;	/* must be 0x10, for the LB */
266 	/* bits 5:0 */
267 	unsigned int	base_dest_nasid:15;	/* nasid of the first bit */
268 	/* bits 20:6 */				/* in uvhub map */
269 	unsigned int	command:8;		/* message type */
270 	/* bits 28:21 */
271 	/* 0x38: SN3net EndPoint Message */
272 	unsigned int	rsvd_1:3;		/* must be zero */
273 	/* bits 31:29 */
274 	/* int will align on 32 bits */
275 	unsigned int	rsvd_2:9;		/* must be zero */
276 	/* bits 40:32 */
277 	/* Suppl_A is 56-41 */
278 	unsigned int	sequence:16;		/* message sequence number */
279 	/* bits 56:41 */			/* becomes bytes 16-17 of msg */
280 						/* Address field (96:57) is
281 						   never used as an address
282 						   (these are address bits
283 						   42:3) */
284 
285 	unsigned int	rsvd_3:1;		/* must be zero */
286 	/* bit 57 */
287 	/* address bits 27:4 are payload */
288 	/* these next 24  (58-81) bits become bytes 12-14 of msg */
289 	/* bits 65:58 land in byte 12 */
290 	unsigned int	replied_to:1;		/* sent as 0 by the source to
291 						   byte 12 */
292 	/* bit 58 */
293 	unsigned int	msg_type:3;		/* software type of the
294 						   message */
295 	/* bits 61:59 */
296 	unsigned int	canceled:1;		/* message canceled, resource
297 						   is to be freed*/
298 	/* bit 62 */
299 	unsigned int	payload_1a:1;		/* not currently used */
300 	/* bit 63 */
301 	unsigned int	payload_1b:2;		/* not currently used */
302 	/* bits 65:64 */
303 
304 	/* bits 73:66 land in byte 13 */
305 	unsigned int	payload_1ca:6;		/* not currently used */
306 	/* bits 71:66 */
307 	unsigned int	payload_1c:2;		/* not currently used */
308 	/* bits 73:72 */
309 
310 	/* bits 81:74 land in byte 14 */
311 	unsigned int	payload_1d:6;		/* not currently used */
312 	/* bits 79:74 */
313 	unsigned int	payload_1e:2;		/* not currently used */
314 	/* bits 81:80 */
315 
316 	unsigned int	rsvd_4:7;		/* must be zero */
317 	/* bits 88:82 */
318 	unsigned int	swack_flag:1;		/* software acknowledge flag */
319 	/* bit 89 */
320 						/* INTD trasactions at
321 						   destination are to wait for
322 						   software acknowledge */
323 	unsigned int	rsvd_5:6;		/* must be zero */
324 	/* bits 95:90 */
325 	unsigned int	rsvd_6:5;		/* must be zero */
326 	/* bits 100:96 */
327 	unsigned int	int_both:1;		/* if 1, interrupt both sockets
328 						   on the uvhub */
329 	/* bit 101*/
330 	unsigned int	fairness:3;		/* usually zero */
331 	/* bits 104:102 */
332 	unsigned int	multilevel:1;		/* multi-level multicast
333 						   format */
334 	/* bit 105 */
335 	/* 0 for TLB: endpoint multi-unicast messages */
336 	unsigned int	chaining:1;		/* next descriptor is part of
337 						   this activation*/
338 	/* bit 106 */
339 	unsigned int	rsvd_7:21;		/* must be zero */
340 	/* bits 127:107 */
341 };
342 
343 /*
344  * UV2 Message header:  16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
345  * see figure 9-2 of harp_sys.pdf
346  * assuming UV3 is the same
347  */
348 struct uv2_3_bau_msg_header {
349 	unsigned int	base_dest_nasid:15;	/* nasid of the first bit */
350 	/* bits 14:0 */				/* in uvhub map */
351 	unsigned int	dest_subnodeid:5;	/* must be 0x10, for the LB */
352 	/* bits 19:15 */
353 	unsigned int	rsvd_1:1;		/* must be zero */
354 	/* bit 20 */
355 	/* Address bits 59:21 */
356 	/* bits 25:2 of address (44:21) are payload */
357 	/* these next 24 bits become bytes 12-14 of msg */
358 	/* bits 28:21 land in byte 12 */
359 	unsigned int	replied_to:1;		/* sent as 0 by the source to
360 						   byte 12 */
361 	/* bit 21 */
362 	unsigned int	msg_type:3;		/* software type of the
363 						   message */
364 	/* bits 24:22 */
365 	unsigned int	canceled:1;		/* message canceled, resource
366 						   is to be freed*/
367 	/* bit 25 */
368 	unsigned int	payload_1:3;		/* not currently used */
369 	/* bits 28:26 */
370 
371 	/* bits 36:29 land in byte 13 */
372 	unsigned int	payload_2a:3;		/* not currently used */
373 	unsigned int	payload_2b:5;		/* not currently used */
374 	/* bits 36:29 */
375 
376 	/* bits 44:37 land in byte 14 */
377 	unsigned int	payload_3:8;		/* not currently used */
378 	/* bits 44:37 */
379 
380 	unsigned int	rsvd_2:7;		/* reserved */
381 	/* bits 51:45 */
382 	unsigned int	swack_flag:1;		/* software acknowledge flag */
383 	/* bit 52 */
384 	unsigned int	rsvd_3a:3;		/* must be zero */
385 	unsigned int	rsvd_3b:8;		/* must be zero */
386 	unsigned int	rsvd_3c:8;		/* must be zero */
387 	unsigned int	rsvd_3d:3;		/* must be zero */
388 	/* bits 74:53 */
389 	unsigned int	fairness:3;		/* usually zero */
390 	/* bits 77:75 */
391 
392 	unsigned int	sequence:16;		/* message sequence number */
393 	/* bits 93:78  Suppl_A  */
394 	unsigned int	chaining:1;		/* next descriptor is part of
395 						   this activation*/
396 	/* bit 94 */
397 	unsigned int	multilevel:1;		/* multi-level multicast
398 						   format */
399 	/* bit 95 */
400 	unsigned int	rsvd_4:24;		/* ordered / source node /
401 						   source subnode / aging
402 						   must be zero */
403 	/* bits 119:96 */
404 	unsigned int	command:8;		/* message type */
405 	/* bits 127:120 */
406 };
407 
408 /*
409  * The activation descriptor:
410  * The format of the message to send, plus all accompanying control
411  * Should be 64 bytes
412  */
413 struct bau_desc {
414 	struct pnmask				distribution;
415 	/*
416 	 * message template, consisting of header and payload:
417 	 */
418 	union bau_msg_header {
419 		struct uv1_bau_msg_header	uv1_hdr;
420 		struct uv2_3_bau_msg_header	uv2_3_hdr;
421 	} header;
422 
423 	union bau_payload_header {
424 		struct uv1_2_3_bau_msg_payload	uv1_2_3;
425 		struct uv4_bau_msg_payload	uv4;
426 	} payload;
427 };
428 /* UV1:
429  *   -payload--    ---------header------
430  *   bytes 0-11    bits 41-56  bits 58-81
431  *       A           B  (2)      C (3)
432  *
433  *            A/B/C are moved to:
434  *       A            C          B
435  *   bytes 0-11  bytes 12-14  bytes 16-17  (byte 15 filled in by hw as vector)
436  *   ------------payload queue-----------
437  */
438 /* UV2:
439  *   -payload--    ---------header------
440  *   bytes 0-11    bits 70-78  bits 21-44
441  *       A           B  (2)      C (3)
442  *
443  *            A/B/C are moved to:
444  *       A            C          B
445  *   bytes 0-11  bytes 12-14  bytes 16-17  (byte 15 filled in by hw as vector)
446  *   ------------payload queue-----------
447  */
448 
449 /*
450  * The payload queue on the destination side is an array of these.
451  * With BAU_MISC_CONTROL set for software acknowledge mode, the messages
452  * are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17
453  * bytes of usable data, including the sw ack vector in byte 15 (bits 127:120)
454  * (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from
455  *  swack_vec and payload_2)
456  * "Enabling Software Acknowledgment mode (see Section 4.3.3 Software
457  *  Acknowledge Processing) also selects 32 byte (17 bytes usable) payload
458  *  operation."
459  */
460 struct bau_pq_entry {
461 	unsigned long	address;	/* signifies a page or all TLB's
462 					   of the cpu */
463 	/* 64 bits, bytes 0-7 */
464 	unsigned short	sending_cpu;	/* cpu that sent the message */
465 	/* 16 bits, bytes 8-9 */
466 	unsigned short	acknowledge_count; /* filled in by destination */
467 	/* 16 bits, bytes 10-11 */
468 	/* these next 3 bytes come from bits 58-81 of the message header */
469 	unsigned short	replied_to:1;	/* sent as 0 by the source */
470 	unsigned short	msg_type:3;	/* software message type */
471 	unsigned short	canceled:1;	/* sent as 0 by the source */
472 	unsigned short	unused1:3;	/* not currently using */
473 	/* byte 12 */
474 	unsigned char	unused2a;	/* not currently using */
475 	/* byte 13 */
476 	unsigned char	unused2;	/* not currently using */
477 	/* byte 14 */
478 	unsigned char	swack_vec;	/* filled in by the hardware */
479 	/* byte 15 (bits 127:120) */
480 	unsigned short	sequence;	/* message sequence number */
481 	/* bytes 16-17 */
482 	unsigned char	unused4[2];	/* not currently using bytes 18-19 */
483 	/* bytes 18-19 */
484 	int		number_of_cpus;	/* filled in at destination */
485 	/* 32 bits, bytes 20-23 (aligned) */
486 	unsigned char	unused5[8];	/* not using */
487 	/* bytes 24-31 */
488 };
489 
490 struct msg_desc {
491 	struct bau_pq_entry	*msg;
492 	int			msg_slot;
493 	struct bau_pq_entry	*queue_first;
494 	struct bau_pq_entry	*queue_last;
495 };
496 
497 struct reset_args {
498 	int			sender;
499 };
500 
501 /*
502  * This structure is allocated per_cpu for UV TLB shootdown statistics.
503  */
504 struct ptc_stats {
505 	/* sender statistics */
506 	unsigned long	s_giveup;		/* number of fall backs to
507 						   IPI-style flushes */
508 	unsigned long	s_requestor;		/* number of shootdown
509 						   requests */
510 	unsigned long	s_stimeout;		/* source side timeouts */
511 	unsigned long	s_dtimeout;		/* destination side timeouts */
512 	unsigned long	s_strongnacks;		/* number of strong nack's */
513 	unsigned long	s_time;			/* time spent in sending side */
514 	unsigned long	s_retriesok;		/* successful retries */
515 	unsigned long	s_ntargcpu;		/* total number of cpu's
516 						   targeted */
517 	unsigned long	s_ntargself;		/* times the sending cpu was
518 						   targeted */
519 	unsigned long	s_ntarglocals;		/* targets of cpus on the local
520 						   blade */
521 	unsigned long	s_ntargremotes;		/* targets of cpus on remote
522 						   blades */
523 	unsigned long	s_ntarglocaluvhub;	/* targets of the local hub */
524 	unsigned long	s_ntargremoteuvhub;	/* remotes hubs targeted */
525 	unsigned long	s_ntarguvhub;		/* total number of uvhubs
526 						   targeted */
527 	unsigned long	s_ntarguvhub16;		/* number of times target
528 						   hubs >= 16*/
529 	unsigned long	s_ntarguvhub8;		/* number of times target
530 						   hubs >= 8 */
531 	unsigned long	s_ntarguvhub4;		/* number of times target
532 						   hubs >= 4 */
533 	unsigned long	s_ntarguvhub2;		/* number of times target
534 						   hubs >= 2 */
535 	unsigned long	s_ntarguvhub1;		/* number of times target
536 						   hubs == 1 */
537 	unsigned long	s_resets_plug;		/* ipi-style resets from plug
538 						   state */
539 	unsigned long	s_resets_timeout;	/* ipi-style resets from
540 						   timeouts */
541 	unsigned long	s_busy;			/* status stayed busy past
542 						   s/w timer */
543 	unsigned long	s_throttles;		/* waits in throttle */
544 	unsigned long	s_retry_messages;	/* retry broadcasts */
545 	unsigned long	s_bau_reenabled;	/* for bau enable/disable */
546 	unsigned long	s_bau_disabled;		/* for bau enable/disable */
547 	unsigned long	s_uv2_wars;		/* uv2 workaround, perm. busy */
548 	unsigned long	s_uv2_wars_hw;		/* uv2 workaround, hiwater */
549 	unsigned long	s_uv2_war_waits;	/* uv2 workaround, long waits */
550 	unsigned long	s_overipilimit;		/* over the ipi reset limit */
551 	unsigned long	s_giveuplimit;		/* disables, over giveup limit*/
552 	unsigned long	s_enters;		/* entries to the driver */
553 	unsigned long	s_ipifordisabled;	/* fall back to IPI; disabled */
554 	unsigned long	s_plugged;		/* plugged by h/w bug*/
555 	unsigned long	s_congested;		/* giveup on long wait */
556 	/* destination statistics */
557 	unsigned long	d_alltlb;		/* times all tlb's on this
558 						   cpu were flushed */
559 	unsigned long	d_onetlb;		/* times just one tlb on this
560 						   cpu was flushed */
561 	unsigned long	d_multmsg;		/* interrupts with multiple
562 						   messages */
563 	unsigned long	d_nomsg;		/* interrupts with no message */
564 	unsigned long	d_time;			/* time spent on destination
565 						   side */
566 	unsigned long	d_requestee;		/* number of messages
567 						   processed */
568 	unsigned long	d_retries;		/* number of retry messages
569 						   processed */
570 	unsigned long	d_canceled;		/* number of messages canceled
571 						   by retries */
572 	unsigned long	d_nocanceled;		/* retries that found nothing
573 						   to cancel */
574 	unsigned long	d_resets;		/* number of ipi-style requests
575 						   processed */
576 	unsigned long	d_rcanceled;		/* number of messages canceled
577 						   by resets */
578 };
579 
580 struct tunables {
581 	int			*tunp;
582 	int			deflt;
583 };
584 
585 struct hub_and_pnode {
586 	short			uvhub;
587 	short			pnode;
588 };
589 
590 struct socket_desc {
591 	short			num_cpus;
592 	short			cpu_number[MAX_CPUS_PER_SOCKET];
593 };
594 
595 struct uvhub_desc {
596 	unsigned short		socket_mask;
597 	short			num_cpus;
598 	short			uvhub;
599 	short			pnode;
600 	struct socket_desc	socket[2];
601 };
602 
603 /**
604  * struct bau_control
605  * @status_mmr: location of status mmr, determined by uvhub_cpu
606  * @status_index: index of ERR|BUSY bits in status mmr, determined by uvhub_cpu
607  *
608  * Per-cpu control struct containing CPU topology information and BAU tuneables.
609  */
610 struct bau_control {
611 	struct bau_desc		*descriptor_base;
612 	struct bau_pq_entry	*queue_first;
613 	struct bau_pq_entry	*queue_last;
614 	struct bau_pq_entry	*bau_msg_head;
615 	struct bau_control	*uvhub_master;
616 	struct bau_control	*socket_master;
617 	struct ptc_stats	*statp;
618 	cpumask_t		*cpumask;
619 	unsigned long		timeout_interval;
620 	unsigned long		set_bau_on_time;
621 	atomic_t		active_descriptor_count;
622 	int			plugged_tries;
623 	int			timeout_tries;
624 	int			ipi_attempts;
625 	int			conseccompletes;
626 	u64			status_mmr;
627 	int			status_index;
628 	bool			nobau;
629 	short			baudisabled;
630 	short			cpu;
631 	short			osnode;
632 	short			uvhub_cpu;
633 	short			uvhub;
634 	short			uvhub_version;
635 	short			cpus_in_socket;
636 	short			cpus_in_uvhub;
637 	short			partition_base_pnode;
638 	short			busy;       /* all were busy (war) */
639 	unsigned short		message_number;
640 	unsigned short		uvhub_quiesce;
641 	short			socket_acknowledge_count[DEST_Q_SIZE];
642 	cycles_t		send_message;
643 	cycles_t		period_end;
644 	cycles_t		period_time;
645 	spinlock_t		uvhub_lock;
646 	spinlock_t		queue_lock;
647 	spinlock_t		disable_lock;
648 	/* tunables */
649 	int			max_concurr;
650 	int			max_concurr_const;
651 	int			plugged_delay;
652 	int			plugsb4reset;
653 	int			timeoutsb4reset;
654 	int			ipi_reset_limit;
655 	int			complete_threshold;
656 	int			cong_response_us;
657 	int			cong_reps;
658 	cycles_t		disabled_period;
659 	int			period_giveups;
660 	int			giveup_limit;
661 	long			period_requests;
662 	struct hub_and_pnode	*thp;
663 };
664 
665 /* Abstracted BAU functions */
666 struct bau_operations {
667 	unsigned long	(*read_l_sw_ack)(void);
668 	unsigned long	(*read_g_sw_ack)(int pnode);
669 	unsigned long	(*bau_gpa_to_offset)(unsigned long vaddr);
670 	void		(*write_l_sw_ack)(unsigned long mmr);
671 	void		(*write_g_sw_ack)(int pnode, unsigned long mmr);
672 	void		(*write_payload_first)(int pnode, unsigned long mmr);
673 	void		(*write_payload_last)(int pnode, unsigned long mmr);
674 	int		(*wait_completion)(struct bau_desc*,
675 				struct bau_control*, long try);
676 };
677 
write_mmr_data_broadcast(int pnode,unsigned long mmr_image)678 static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
679 {
680 	write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
681 }
682 
write_mmr_descriptor_base(int pnode,unsigned long mmr_image)683 static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
684 {
685 	write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
686 }
687 
write_mmr_activation(unsigned long index)688 static inline void write_mmr_activation(unsigned long index)
689 {
690 	write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
691 }
692 
write_gmmr_activation(int pnode,unsigned long mmr_image)693 static inline void write_gmmr_activation(int pnode, unsigned long mmr_image)
694 {
695 	write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
696 }
697 
write_mmr_proc_payload_first(int pnode,unsigned long mmr_image)698 static inline void write_mmr_proc_payload_first(int pnode, unsigned long mmr_image)
699 {
700 	write_gmmr(pnode, UV4H_LB_PROC_INTD_QUEUE_FIRST, mmr_image);
701 }
702 
write_mmr_proc_payload_last(int pnode,unsigned long mmr_image)703 static inline void write_mmr_proc_payload_last(int pnode, unsigned long mmr_image)
704 {
705 	write_gmmr(pnode, UV4H_LB_PROC_INTD_QUEUE_LAST, mmr_image);
706 }
707 
write_mmr_payload_first(int pnode,unsigned long mmr_image)708 static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image)
709 {
710 	write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
711 }
712 
write_mmr_payload_tail(int pnode,unsigned long mmr_image)713 static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
714 {
715 	write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
716 }
717 
write_mmr_payload_last(int pnode,unsigned long mmr_image)718 static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image)
719 {
720 	write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
721 }
722 
write_mmr_misc_control(int pnode,unsigned long mmr_image)723 static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image)
724 {
725 	write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
726 }
727 
read_mmr_misc_control(int pnode)728 static inline unsigned long read_mmr_misc_control(int pnode)
729 {
730 	return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
731 }
732 
write_mmr_sw_ack(unsigned long mr)733 static inline void write_mmr_sw_ack(unsigned long mr)
734 {
735 	uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
736 }
737 
write_gmmr_sw_ack(int pnode,unsigned long mr)738 static inline void write_gmmr_sw_ack(int pnode, unsigned long mr)
739 {
740 	write_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
741 }
742 
read_mmr_sw_ack(void)743 static inline unsigned long read_mmr_sw_ack(void)
744 {
745 	return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
746 }
747 
read_gmmr_sw_ack(int pnode)748 static inline unsigned long read_gmmr_sw_ack(int pnode)
749 {
750 	return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
751 }
752 
write_mmr_proc_sw_ack(unsigned long mr)753 static inline void write_mmr_proc_sw_ack(unsigned long mr)
754 {
755 	uv_write_local_mmr(UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR, mr);
756 }
757 
write_gmmr_proc_sw_ack(int pnode,unsigned long mr)758 static inline void write_gmmr_proc_sw_ack(int pnode, unsigned long mr)
759 {
760 	write_gmmr(pnode, UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR, mr);
761 }
762 
read_mmr_proc_sw_ack(void)763 static inline unsigned long read_mmr_proc_sw_ack(void)
764 {
765 	return read_lmmr(UV4H_LB_PROC_INTD_SOFT_ACK_PENDING);
766 }
767 
read_gmmr_proc_sw_ack(int pnode)768 static inline unsigned long read_gmmr_proc_sw_ack(int pnode)
769 {
770 	return read_gmmr(pnode, UV4H_LB_PROC_INTD_SOFT_ACK_PENDING);
771 }
772 
write_mmr_data_config(int pnode,unsigned long mr)773 static inline void write_mmr_data_config(int pnode, unsigned long mr)
774 {
775 	uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
776 }
777 
bau_uvhub_isset(int uvhub,struct pnmask * dstp)778 static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp)
779 {
780 	return constant_test_bit(uvhub, &dstp->bits[0]);
781 }
bau_uvhub_set(int pnode,struct pnmask * dstp)782 static inline void bau_uvhub_set(int pnode, struct pnmask *dstp)
783 {
784 	__set_bit(pnode, &dstp->bits[0]);
785 }
bau_uvhubs_clear(struct pnmask * dstp,int nbits)786 static inline void bau_uvhubs_clear(struct pnmask *dstp,
787 				    int nbits)
788 {
789 	bitmap_zero(&dstp->bits[0], nbits);
790 }
bau_uvhub_weight(struct pnmask * dstp)791 static inline int bau_uvhub_weight(struct pnmask *dstp)
792 {
793 	return bitmap_weight((unsigned long *)&dstp->bits[0],
794 				UV_DISTRIBUTION_SIZE);
795 }
796 
bau_cpubits_clear(struct bau_local_cpumask * dstp,int nbits)797 static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
798 {
799 	bitmap_zero(&dstp->bits, nbits);
800 }
801 
802 extern void uv_bau_message_intr1(void);
803 #ifdef CONFIG_TRACING
804 #define trace_uv_bau_message_intr1 uv_bau_message_intr1
805 #endif
806 extern void uv_bau_timeout_intr1(void);
807 
808 struct atomic_short {
809 	short counter;
810 };
811 
812 /*
813  * atomic_read_short - read a short atomic variable
814  * @v: pointer of type atomic_short
815  *
816  * Atomically reads the value of @v.
817  */
atomic_read_short(const struct atomic_short * v)818 static inline int atomic_read_short(const struct atomic_short *v)
819 {
820 	return v->counter;
821 }
822 
823 /*
824  * atom_asr - add and return a short int
825  * @i: short value to add
826  * @v: pointer of type atomic_short
827  *
828  * Atomically adds @i to @v and returns @i + @v
829  */
atom_asr(short i,struct atomic_short * v)830 static inline int atom_asr(short i, struct atomic_short *v)
831 {
832 	short __i = i;
833 	asm volatile(LOCK_PREFIX "xaddw %0, %1"
834 			: "+r" (i), "+m" (v->counter)
835 			: : "memory");
836 	return i + __i;
837 }
838 
839 /*
840  * conditionally add 1 to *v, unless *v is >= u
841  * return 0 if we cannot add 1 to *v because it is >= u
842  * return 1 if we can add 1 to *v because it is < u
843  * the add is atomic
844  *
845  * This is close to atomic_add_unless(), but this allows the 'u' value
846  * to be lowered below the current 'v'.  atomic_add_unless can only stop
847  * on equal.
848  */
atomic_inc_unless_ge(spinlock_t * lock,atomic_t * v,int u)849 static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
850 {
851 	spin_lock(lock);
852 	if (atomic_read(v) >= u) {
853 		spin_unlock(lock);
854 		return 0;
855 	}
856 	atomic_inc(v);
857 	spin_unlock(lock);
858 	return 1;
859 }
860 
861 #endif /* _ASM_X86_UV_UV_BAU_H */
862