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Searched refs:BIT10 (Results 1 – 19 of 19) sorted by relevance

/drivers/staging/emxx_udc/
Demxx_udc.h66 #define BIT10 0x00000400 macro
91 #define INT_SEL BIT10
150 #define EP2_INT BIT10
177 #define EP2_EN BIT10
218 #define EP0_IN_DATA BIT10
271 #define EPN_OPIDCLR BIT10
303 #define EPN_IPID BIT10 /* R */
334 #define EPN_DEND_SET BIT10
/drivers/staging/rtl8723bs/include/
Dhal_com_reg.h618 #define RRSR_48M BIT10
794 #define IMR_ATIMEND BIT10 /* For 92C, ATIM Window End Interrupt. For 8723 and later ICs, it al…
810 #define IMR_RXERR BIT10
842 #define PHIMR_C2HCMD BIT10
865 #define PHIMR_RXERR BIT10
893 #define UHIMR_C2HCMD BIT10
918 #define UHIMR_RXERR BIT10
947 #define IMR_C2HCMD_88E BIT10 /* CPU to Host Command INT Status, Write 1 clear */
976 #define IMR_RXERR_88E BIT10 /* Rx Error Flag INT Status, Write 1 clear */
1041 #define RCR_RSVD_BIT10 BIT10 /* Reserved */
Drtl8723b_spec.h216 #define IMR_C2HCMD_8723B BIT10 /* CPU to Host Command INT Status, Write 1 clear */
245 #define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, Write 1 clear */
Dosdep_service.h31 #define BIT10 0x00000400 macro
Drtw_mlme_ext.h54 #define DYNAMIC_BB_PATH_DIV BIT10/* ODM_BB_PATH_DIV */
/drivers/staging/rtl8723bs/hal/
Drtl8723b_rf6052.c65 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10 | BIT11); in PHY_RF6052SetBandwidth8723B()
71 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10); in PHY_RF6052SetBandwidth8723B()
DHal8723BReg.h398 #define IMR_C2HCMD_8723B BIT10 /* CPU to Host Command INT Status, Write 1 clear */
427 #define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, Write 1 clear */
Dodm_debug.h71 #define ODM_COMP_PATH_DIV BIT10
Dodm.h432 ODM_BB_PATH_DIV = BIT10,
Dodm_DIG.c24 …PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); /* 0x890[9:8]=3 … in odm_NHMCounterStatisticsInit()
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h218 #define IMR_RXCMDOK BIT10
241 #define TPPoll_StopBE BIT10
371 #define RRSR_48M BIT10
/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbt_precomp.h41 #define BIT10 0x00000400 macro
/drivers/staging/rtl8192e/
Drtl819x_Qos.h20 #define BIT10 0x00000400 macro
/drivers/scsi/
Ddc395x.h66 #define BIT10 0x00000400 macro
/drivers/tty/
Dsynclink_gt.c415 #define IRQ_RXDATA BIT10
2108 if (count == info->rbuf_fill_level || (reg & BIT10)) { in isr_rxdata()
4275 case HDLC_ENCODING_NRZB: val |= BIT10; break; in sync_mode()
4277 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode()
4279 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()
4281 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
4348 case HDLC_ENCODING_NRZB: val |= BIT10; break; in sync_mode()
4350 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode()
4352 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()
4354 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
Dsynclink.c562 #define MISCSTATUS_RI BIT10
584 #define SICR_RI_INACTIVE BIT10
585 #define SICR_RI (BIT11|BIT10)
1705 else if ( (DmaVector&(BIT10|BIT9)) == BIT10) in mgsl_interrupt()
4696 RegValue |= ( BIT12 | BIT10 | BIT9 ); in usc_set_sdlc_mode()
4771 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()
4895 RegValue |= BIT10; in usc_set_sdlc_mode()
5090 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break; in usc_set_sdlc_mode()
5092 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 | BIT10; break; in usc_set_sdlc_mode()
/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
Dreg.h368 #define RRSR_48M BIT10
/drivers/scsi/lpfc/
Dlpfc_hw4.h719 #define LPFC_SLI4_INTR10 BIT10
/drivers/char/pcmcia/
Dsynclink_cs.c295 #define IRQ_CTS BIT10 // CTS status change