1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * EMXX FCD (Function Controller Driver) for USB. 4 * 5 * Copyright (C) 2010 Renesas Electronics Corporation 6 */ 7 8 #ifndef _LINUX_EMXX_H 9 #define _LINUX_EMXX_H 10 11 /*---------------------------------------------------------------------------*/ 12 /*----------------- Default undef */ 13 #if 0 14 #define DEBUG 15 #define UDC_DEBUG_DUMP 16 #endif 17 18 /*----------------- Default define */ 19 #define USE_DMA 1 20 #define USE_SUSPEND_WAIT 1 21 22 /*------------ Board dependence(Resource) */ 23 #define VBUS_VALUE GPIO_VBUS 24 25 /* below hacked up for staging integration */ 26 #define GPIO_VBUS 0 /* GPIO_P153 on KZM9D */ 27 #define INT_VBUS 0 /* IRQ for GPIO_P153 */ 28 struct gpio_desc *vbus_gpio; 29 int vbus_irq; 30 31 /*------------ Board dependence(Wait) */ 32 33 /* CHATTERING wait time ms */ 34 #define VBUS_CHATTERING_MDELAY 1 35 /* DMA Abort wait time ms */ 36 #define DMA_DISABLE_TIME 10 37 38 /*------------ Controller dependence */ 39 #define NUM_ENDPOINTS 14 /* Endpoint */ 40 #define REG_EP_NUM 15 /* Endpoint Register */ 41 #define DMA_MAX_COUNT 256 /* DMA Block */ 42 43 #define EPC_RST_DISABLE_TIME 1 /* 1 usec */ 44 #define EPC_DIRPD_DISABLE_TIME 1 /* 1 msec */ 45 #define EPC_PLL_LOCK_COUNT 1000 /* 1000 */ 46 #define IN_DATA_EMPTY_COUNT 1000 /* 1000 */ 47 48 #define CHATGER_TIME 700 /* 700msec */ 49 #define USB_SUSPEND_TIME 2000 /* 2 sec */ 50 51 /* U2F FLAG */ 52 #define U2F_ENABLE 1 53 #define U2F_DISABLE 0 54 55 /*------- BIT */ 56 #define BIT00 0x00000001 57 #define BIT01 0x00000002 58 #define BIT02 0x00000004 59 #define BIT03 0x00000008 60 #define BIT04 0x00000010 61 #define BIT05 0x00000020 62 #define BIT06 0x00000040 63 #define BIT07 0x00000080 64 #define BIT08 0x00000100 65 #define BIT09 0x00000200 66 #define BIT10 0x00000400 67 #define BIT11 0x00000800 68 #define BIT12 0x00001000 69 #define BIT13 0x00002000 70 #define BIT14 0x00004000 71 #define BIT15 0x00008000 72 #define BIT16 0x00010000 73 #define BIT17 0x00020000 74 #define BIT18 0x00040000 75 #define BIT19 0x00080000 76 #define BIT20 0x00100000 77 #define BIT21 0x00200000 78 #define BIT22 0x00400000 79 #define BIT23 0x00800000 80 #define BIT24 0x01000000 81 #define BIT25 0x02000000 82 #define BIT26 0x04000000 83 #define BIT27 0x08000000 84 #define BIT28 0x10000000 85 #define BIT29 0x20000000 86 #define BIT30 0x40000000 87 #define BIT31 0x80000000 88 89 #define TEST_FORCE_ENABLE (BIT18 + BIT16) 90 91 #define INT_SEL BIT10 92 #define CONSTFS BIT09 93 #define SOF_RCV BIT08 94 #define RSUM_IN BIT07 95 #define SUSPEND BIT06 96 #define CONF BIT05 97 #define DEFAULT BIT04 98 #define CONNECTB BIT03 99 #define PUE2 BIT02 100 101 #define MAX_TEST_MODE_NUM 0x05 102 #define TEST_MODE_SHIFT 16 103 104 /*------- (0x0004) USB Status Register */ 105 #define SPEED_MODE BIT06 106 #define HIGH_SPEED BIT06 107 108 #define CONF BIT05 109 #define DEFAULT BIT04 110 #define USB_RST BIT03 111 #define SPND_OUT BIT02 112 #define RSUM_OUT BIT01 113 114 /*------- (0x0008) USB Address Register */ 115 #define USB_ADDR 0x007F0000 116 #define SOF_STATUS BIT15 117 #define UFRAME (BIT14 + BIT13 + BIT12) 118 #define FRAME 0x000007FF 119 120 #define USB_ADRS_SHIFT 16 121 122 /*------- (0x000C) UTMI Characteristic 1 Register */ 123 #define SQUSET (BIT07 + BIT06 + BIT05 + BIT04) 124 125 #define USB_SQUSET (BIT06 + BIT05 + BIT04) 126 127 /*------- (0x0010) TEST Control Register */ 128 #define FORCEHS BIT02 129 #define CS_TESTMODEEN BIT01 130 #define LOOPBACK BIT00 131 132 /*------- (0x0018) Setup Data 0 Register */ 133 /*------- (0x001C) Setup Data 1 Register */ 134 135 /*------- (0x0020) USB Interrupt Status Register */ 136 #define EPN_INT 0x00FFFF00 137 #define EP15_INT BIT23 138 #define EP14_INT BIT22 139 #define EP13_INT BIT21 140 #define EP12_INT BIT20 141 #define EP11_INT BIT19 142 #define EP10_INT BIT18 143 #define EP9_INT BIT17 144 #define EP8_INT BIT16 145 #define EP7_INT BIT15 146 #define EP6_INT BIT14 147 #define EP5_INT BIT13 148 #define EP4_INT BIT12 149 #define EP3_INT BIT11 150 #define EP2_INT BIT10 151 #define EP1_INT BIT09 152 #define EP0_INT BIT08 153 #define SPEED_MODE_INT BIT06 154 #define SOF_ERROR_INT BIT05 155 #define SOF_INT BIT04 156 #define USB_RST_INT BIT03 157 #define SPND_INT BIT02 158 #define RSUM_INT BIT01 159 160 #define USB_INT_STA_RW 0x7E 161 162 /*------- (0x0024) USB Interrupt Enable Register */ 163 #define EP15_0_EN 0x00FFFF00 164 #define EP15_EN BIT23 165 #define EP14_EN BIT22 166 #define EP13_EN BIT21 167 #define EP12_EN BIT20 168 #define EP11_EN BIT19 169 #define EP10_EN BIT18 170 #define EP9_EN BIT17 171 #define EP8_EN BIT16 172 #define EP7_EN BIT15 173 #define EP6_EN BIT14 174 #define EP5_EN BIT13 175 #define EP4_EN BIT12 176 #define EP3_EN BIT11 177 #define EP2_EN BIT10 178 #define EP1_EN BIT09 179 #define EP0_EN BIT08 180 #define SPEED_MODE_EN BIT06 181 #define SOF_ERROR_EN BIT05 182 #define SOF_EN BIT04 183 #define USB_RST_EN BIT03 184 #define SPND_EN BIT02 185 #define RSUM_EN BIT01 186 187 #define USB_INT_EN_BIT \ 188 (EP0_EN | SPEED_MODE_EN | USB_RST_EN | SPND_EN | RSUM_EN) 189 190 /*------- (0x0028) EP0 Control Register */ 191 #define EP0_STGSEL BIT18 192 #define EP0_OVERSEL BIT17 193 #define EP0_AUTO BIT16 194 #define EP0_PIDCLR BIT09 195 #define EP0_BCLR BIT08 196 #define EP0_DEND BIT07 197 #define EP0_DW (BIT06 + BIT05) 198 #define EP0_DW4 0 199 #define EP0_DW3 (BIT06 + BIT05) 200 #define EP0_DW2 BIT06 201 #define EP0_DW1 BIT05 202 203 #define EP0_INAK_EN BIT04 204 #define EP0_PERR_NAK_CLR BIT03 205 #define EP0_STL BIT02 206 #define EP0_INAK BIT01 207 #define EP0_ONAK BIT00 208 209 /*------- (0x002C) EP0 Status Register */ 210 #define EP0_PID BIT18 211 #define EP0_PERR_NAK BIT17 212 #define EP0_PERR_NAK_INT BIT16 213 #define EP0_OUT_NAK_INT BIT15 214 #define EP0_OUT_NULL BIT14 215 #define EP0_OUT_FULL BIT13 216 #define EP0_OUT_EMPTY BIT12 217 #define EP0_IN_NAK_INT BIT11 218 #define EP0_IN_DATA BIT10 219 #define EP0_IN_FULL BIT09 220 #define EP0_IN_EMPTY BIT08 221 #define EP0_OUT_NULL_INT BIT07 222 #define EP0_OUT_OR_INT BIT06 223 #define EP0_OUT_INT BIT05 224 #define EP0_IN_INT BIT04 225 #define EP0_STALL_INT BIT03 226 #define STG_END_INT BIT02 227 #define STG_START_INT BIT01 228 #define SETUP_INT BIT00 229 230 #define EP0_STATUS_RW_BIT (BIT16 | BIT15 | BIT11 | 0xFF) 231 232 /*------- (0x0030) EP0 Interrupt Enable Register */ 233 #define EP0_PERR_NAK_EN BIT16 234 #define EP0_OUT_NAK_EN BIT15 235 236 #define EP0_IN_NAK_EN BIT11 237 238 #define EP0_OUT_NULL_EN BIT07 239 #define EP0_OUT_OR_EN BIT06 240 #define EP0_OUT_EN BIT05 241 #define EP0_IN_EN BIT04 242 #define EP0_STALL_EN BIT03 243 #define STG_END_EN BIT02 244 #define STG_START_EN BIT01 245 #define SETUP_EN BIT00 246 247 #define EP0_INT_EN_BIT \ 248 (EP0_OUT_OR_EN | EP0_OUT_EN | EP0_IN_EN | STG_END_EN | SETUP_EN) 249 250 /*------- (0x0034) EP0 Length Register */ 251 #define EP0_LDATA 0x0000007F 252 253 /*------- (0x0038) EP0 Read Register */ 254 /*------- (0x003C) EP0 Write Register */ 255 256 /*------- (0x0040:) EPN Control Register */ 257 #define EPN_EN BIT31 258 #define EPN_BUF_TYPE BIT30 259 #define EPN_BUF_SINGLE BIT30 260 261 #define EPN_DIR0 BIT26 262 #define EPN_MODE (BIT25 + BIT24) 263 #define EPN_BULK 0 264 #define EPN_INTERRUPT BIT24 265 #define EPN_ISO BIT25 266 267 #define EPN_OVERSEL BIT17 268 #define EPN_AUTO BIT16 269 270 #define EPN_IPIDCLR BIT11 271 #define EPN_OPIDCLR BIT10 272 #define EPN_BCLR BIT09 273 #define EPN_CBCLR BIT08 274 #define EPN_DEND BIT07 275 #define EPN_DW (BIT06 + BIT05) 276 #define EPN_DW4 0 277 #define EPN_DW3 (BIT06 + BIT05) 278 #define EPN_DW2 BIT06 279 #define EPN_DW1 BIT05 280 281 #define EPN_OSTL_EN BIT04 282 #define EPN_ISTL BIT03 283 #define EPN_OSTL BIT02 284 285 #define EPN_ONAK BIT00 286 287 /*------- (0x0044:) EPN Status Register */ 288 #define EPN_ISO_PIDERR BIT29 /* R */ 289 #define EPN_OPID BIT28 /* R */ 290 #define EPN_OUT_NOTKN BIT27 /* R */ 291 #define EPN_ISO_OR BIT26 /* R */ 292 293 #define EPN_ISO_CRC BIT24 /* R */ 294 #define EPN_OUT_END_INT BIT23 /* RW */ 295 #define EPN_OUT_OR_INT BIT22 /* RW */ 296 #define EPN_OUT_NAK_ERR_INT BIT21 /* RW */ 297 #define EPN_OUT_STALL_INT BIT20 /* RW */ 298 #define EPN_OUT_INT BIT19 /* RW */ 299 #define EPN_OUT_NULL_INT BIT18 /* RW */ 300 #define EPN_OUT_FULL BIT17 /* R */ 301 #define EPN_OUT_EMPTY BIT16 /* R */ 302 303 #define EPN_IPID BIT10 /* R */ 304 #define EPN_IN_NOTKN BIT09 /* R */ 305 #define EPN_ISO_UR BIT08 /* R */ 306 #define EPN_IN_END_INT BIT07 /* RW */ 307 308 #define EPN_IN_NAK_ERR_INT BIT05 /* RW */ 309 #define EPN_IN_STALL_INT BIT04 /* RW */ 310 #define EPN_IN_INT BIT03 /* RW */ 311 #define EPN_IN_DATA BIT02 /* R */ 312 #define EPN_IN_FULL BIT01 /* R */ 313 #define EPN_IN_EMPTY BIT00 /* R */ 314 315 #define EPN_INT_EN \ 316 (EPN_OUT_END_INT | EPN_OUT_INT | EPN_IN_END_INT | EPN_IN_INT) 317 318 /*------- (0x0048:) EPN Interrupt Enable Register */ 319 #define EPN_OUT_END_EN BIT23 /* RW */ 320 #define EPN_OUT_OR_EN BIT22 /* RW */ 321 #define EPN_OUT_NAK_ERR_EN BIT21 /* RW */ 322 #define EPN_OUT_STALL_EN BIT20 /* RW */ 323 #define EPN_OUT_EN BIT19 /* RW */ 324 #define EPN_OUT_NULL_EN BIT18 /* RW */ 325 326 #define EPN_IN_END_EN BIT07 /* RW */ 327 328 #define EPN_IN_NAK_ERR_EN BIT05 /* RW */ 329 #define EPN_IN_STALL_EN BIT04 /* RW */ 330 #define EPN_IN_EN BIT03 /* RW */ 331 332 /*------- (0x004C:) EPN Interrupt Enable Register */ 333 #define EPN_STOP_MODE BIT11 334 #define EPN_DEND_SET BIT10 335 #define EPN_BURST_SET BIT09 336 #define EPN_STOP_SET BIT08 337 338 #define EPN_DMA_EN BIT04 339 340 #define EPN_DMAMODE0 BIT00 341 342 /*------- (0x0050:) EPN MaxPacket & BaseAddress Register */ 343 #define EPN_BASEAD 0x1FFF0000 344 #define EPN_MPKT 0x000007FF 345 346 /*------- (0x0054:) EPN Length & DMA Count Register */ 347 #define EPN_DMACNT 0x01FF0000 348 #define EPN_LDATA 0x000007FF 349 350 /*------- (0x0058:) EPN Read Register */ 351 /*------- (0x005C:) EPN Write Register */ 352 353 /*------- (0x1000) AHBSCTR Register */ 354 #define WAIT_MODE BIT00 355 356 /*------- (0x1004) AHBMCTR Register */ 357 #define ARBITER_CTR BIT31 /* RW */ 358 #define MCYCLE_RST BIT12 /* RW */ 359 360 #define ENDIAN_CTR (BIT09 + BIT08) /* RW */ 361 #define ENDIAN_BYTE_SWAP BIT09 362 #define ENDIAN_HALF_WORD_SWAP ENDIAN_CTR 363 364 #define HBUSREQ_MODE BIT05 /* RW */ 365 #define HTRANS_MODE BIT04 /* RW */ 366 367 #define WBURST_TYPE BIT02 /* RW */ 368 #define BURST_TYPE (BIT01 + BIT00) /* RW */ 369 #define BURST_MAX_16 0 370 #define BURST_MAX_8 BIT00 371 #define BURST_MAX_4 BIT01 372 #define BURST_SINGLE BURST_TYPE 373 374 /*------- (0x1008) AHBBINT Register */ 375 #define DMA_ENDINT 0xFFFE0000 /* RW */ 376 377 #define AHB_VBUS_INT BIT13 /* RW */ 378 379 #define MBUS_ERRINT BIT06 /* RW */ 380 381 #define SBUS_ERRINT0 BIT04 /* RW */ 382 #define ERR_MASTER 0x0000000F /* R */ 383 384 /*------- (0x100C) AHBBINTEN Register */ 385 #define DMA_ENDINTEN 0xFFFE0000 /* RW */ 386 387 #define VBUS_INTEN BIT13 /* RW */ 388 389 #define MBUS_ERRINTEN BIT06 /* RW */ 390 391 #define SBUS_ERRINT0EN BIT04 /* RW */ 392 393 /*------- (0x1010) EPCTR Register */ 394 #define DIRPD BIT12 /* RW */ 395 396 #define VBUS_LEVEL BIT08 /* R */ 397 398 #define PLL_RESUME BIT05 /* RW */ 399 #define PLL_LOCK BIT04 /* R */ 400 401 #define EPC_RST BIT00 /* RW */ 402 403 /*------- (0x1014) USBF_EPTEST Register */ 404 #define LINESTATE (BIT09 + BIT08) /* R */ 405 #define DM_LEVEL BIT09 /* R */ 406 #define DP_LEVEL BIT08 /* R */ 407 408 #define PHY_TST BIT01 /* RW */ 409 #define PHY_TSTCLK BIT00 /* RW */ 410 411 /*------- (0x1020) USBSSVER Register */ 412 #define AHBB_VER 0x00FF0000 /* R */ 413 #define EPC_VER 0x0000FF00 /* R */ 414 #define SS_VER 0x000000FF /* R */ 415 416 /*------- (0x1024) USBSSCONF Register */ 417 #define EP_AVAILABLE 0xFFFF0000 /* R */ 418 #define DMA_AVAILABLE 0x0000FFFF /* R */ 419 420 /*------- (0x1110:) EPNDCR1 Register */ 421 #define DCR1_EPN_DMACNT 0x00FF0000 /* RW */ 422 423 #define DCR1_EPN_DIR0 BIT01 /* RW */ 424 #define DCR1_EPN_REQEN BIT00 /* RW */ 425 426 /*------- (0x1114:) EPNDCR2 Register */ 427 #define DCR2_EPN_LMPKT 0x07FF0000 /* RW */ 428 429 #define DCR2_EPN_MPKT 0x000007FF /* RW */ 430 431 /*------- (0x1118:) EPNTADR Register */ 432 #define EPN_TADR 0xFFFFFFFF /* RW */ 433 434 /*===========================================================================*/ 435 /* Struct */ 436 /*------- ep_regs */ 437 struct ep_regs { 438 u32 EP_CONTROL; /* EP Control */ 439 u32 EP_STATUS; /* EP Status */ 440 u32 EP_INT_ENA; /* EP Interrupt Enable */ 441 u32 EP_DMA_CTRL; /* EP DMA Control */ 442 u32 EP_PCKT_ADRS; /* EP Maxpacket & BaseAddress */ 443 u32 EP_LEN_DCNT; /* EP Length & DMA count */ 444 u32 EP_READ; /* EP Read */ 445 u32 EP_WRITE; /* EP Write */ 446 }; 447 448 /*------- ep_dcr */ 449 struct ep_dcr { 450 u32 EP_DCR1; /* EP_DCR1 */ 451 u32 EP_DCR2; /* EP_DCR2 */ 452 u32 EP_TADR; /* EP_TADR */ 453 u32 Reserved; /* Reserved */ 454 }; 455 456 /*------- Function Registers */ 457 struct fc_regs { 458 u32 USB_CONTROL; /* (0x0000) USB Control */ 459 u32 USB_STATUS; /* (0x0004) USB Status */ 460 u32 USB_ADDRESS; /* (0x0008) USB Address */ 461 u32 UTMI_CHARACTER_1; /* (0x000C) UTMI Setting */ 462 u32 TEST_CONTROL; /* (0x0010) TEST Control */ 463 u32 reserved_14; /* (0x0014) Reserved */ 464 u32 SETUP_DATA0; /* (0x0018) Setup Data0 */ 465 u32 SETUP_DATA1; /* (0x001C) Setup Data1 */ 466 u32 USB_INT_STA; /* (0x0020) USB Interrupt Status */ 467 u32 USB_INT_ENA; /* (0x0024) USB Interrupt Enable */ 468 u32 EP0_CONTROL; /* (0x0028) EP0 Control */ 469 u32 EP0_STATUS; /* (0x002C) EP0 Status */ 470 u32 EP0_INT_ENA; /* (0x0030) EP0 Interrupt Enable */ 471 u32 EP0_LENGTH; /* (0x0034) EP0 Length */ 472 u32 EP0_READ; /* (0x0038) EP0 Read */ 473 u32 EP0_WRITE; /* (0x003C) EP0 Write */ 474 475 struct ep_regs EP_REGS[REG_EP_NUM]; /* Endpoint Register */ 476 477 u8 reserved_220[0x1000 - 0x220]; /* (0x0220:0x0FFF) Reserved */ 478 479 u32 AHBSCTR; /* (0x1000) AHBSCTR */ 480 u32 AHBMCTR; /* (0x1004) AHBMCTR */ 481 u32 AHBBINT; /* (0x1008) AHBBINT */ 482 u32 AHBBINTEN; /* (0x100C) AHBBINTEN */ 483 u32 EPCTR; /* (0x1010) EPCTR */ 484 u32 USBF_EPTEST; /* (0x1014) USBF_EPTEST */ 485 486 u8 reserved_1018[0x20 - 0x18]; /* (0x1018:0x101F) Reserved */ 487 488 u32 USBSSVER; /* (0x1020) USBSSVER */ 489 u32 USBSSCONF; /* (0x1024) USBSSCONF */ 490 491 u8 reserved_1028[0x110 - 0x28]; /* (0x1028:0x110F) Reserved */ 492 493 struct ep_dcr EP_DCR[REG_EP_NUM]; /* */ 494 495 u8 reserved_1200[0x1000 - 0x200]; /* Reserved */ 496 } __aligned(32); 497 498 #define EP0_PACKETSIZE 64 499 #define EP_PACKETSIZE 1024 500 501 /* EPN RAM SIZE */ 502 #define D_RAM_SIZE_CTRL 64 503 504 /* EPN Bulk Endpoint Max Packet Size */ 505 #define D_FS_RAM_SIZE_BULK 64 506 #define D_HS_RAM_SIZE_BULK 512 507 508 struct nbu2ss_udc; 509 510 enum ep0_state { 511 EP0_IDLE, 512 EP0_IN_DATA_PHASE, 513 EP0_OUT_DATA_PHASE, 514 EP0_IN_STATUS_PHASE, 515 EP0_OUT_STATUS_PAHSE, 516 EP0_END_XFER, 517 EP0_SUSPEND, 518 EP0_STALL, 519 }; 520 521 struct nbu2ss_req { 522 struct usb_request req; 523 struct list_head queue; 524 525 u32 div_len; 526 bool dma_flag; 527 bool zero; 528 529 bool unaligned; 530 531 unsigned mapped:1; 532 }; 533 534 struct nbu2ss_ep { 535 struct usb_ep ep; 536 struct list_head queue; 537 538 struct nbu2ss_udc *udc; 539 540 const struct usb_endpoint_descriptor *desc; 541 542 u8 epnum; 543 u8 direct; 544 u8 ep_type; 545 546 unsigned wedged:1; 547 unsigned halted:1; 548 unsigned stalled:1; 549 550 u8 *virt_buf; 551 dma_addr_t phys_buf; 552 }; 553 554 struct nbu2ss_udc { 555 struct usb_gadget gadget; 556 struct usb_gadget_driver *driver; 557 struct platform_device *pdev; 558 struct device *dev; 559 spinlock_t lock; /* Protects nbu2ss_udc structure fields */ 560 struct completion *pdone; 561 562 enum ep0_state ep0state; 563 enum usb_device_state devstate; 564 struct usb_ctrlrequest ctrl; 565 struct nbu2ss_req ep0_req; 566 u8 ep0_buf[EP0_PACKETSIZE]; 567 568 struct nbu2ss_ep ep[NUM_ENDPOINTS]; 569 570 unsigned softconnect:1; 571 unsigned vbus_active:1; 572 unsigned linux_suspended:1; 573 unsigned linux_resume:1; 574 unsigned usb_suspended:1; 575 unsigned remote_wakeup:1; 576 unsigned udc_enabled:1; 577 578 unsigned int mA; 579 580 u32 curr_config; /* Current Configuration Number */ 581 582 struct fc_regs __iomem *p_regs; 583 }; 584 585 /* USB register access structure */ 586 union usb_reg_access { 587 struct { 588 unsigned char DATA[4]; 589 } byte; 590 unsigned int dw; 591 }; 592 593 /*-------------------------------------------------------------------------*/ 594 595 #endif /* _LINUX_EMXX_H */ 596