Searched refs:BIT18 (Results 1 – 12 of 12) sorted by relevance
74 #define BIT18 0x00040000 macro89 #define TEST_FORCE_ENABLE (BIT18 + BIT16)142 #define EP10_INT BIT18169 #define EP10_EN BIT18191 #define EP0_STGSEL BIT18210 #define EP0_PID BIT18299 #define EPN_OUT_NULL_INT BIT18 /* RW */324 #define EPN_OUT_NULL_EN BIT18 /* RW */
626 #define RRSR_MCS6 BIT18786 #define IMR_BCNDOK1 BIT18 /* Beacon Queue DMA OK Interrup 1 */834 #define PHIMR_BCNDOK2 BIT18860 #define PHIMR_BCNDOK6 BIT18885 #define UHIMR_BCNDOK2 BIT18911 #define UHIMR_BCNDOK6 BIT18969 #define IMR_BCNDOK5_88E BIT18 /* Beacon Queue DMA OK Interrup 5 */1033 #define RCR_TIM_PARSER_EN BIT18 /* RX Beacon TIM Parser. */1577 #define SDIO_HIMR_CPWM1_MSK BIT181603 #define SDIO_HISR_CPWM1 BIT18[all …]
238 #define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrupt 5 */
39 #define BIT18 0x00040000 macro
131 BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23)142 #define RCR_ADF BIT18379 #define RRSR_MCS6 BIT18
49 #define BIT18 0x00040000 macro
28 #define BIT18 0x00040000 macro
420 #define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrup 5 */
1725 PHY_SetRFReg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18|BIT17|BIT16|BIT15, target); in rtw_bb_rf_gain_offset()
58 #define BIT18 0x00040000 macro
376 #define RRSR_MCS6 BIT18
727 #define LPFC_SLI4_INTR18 BIT18