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Searched refs:BIT_0 (Results 1 – 25 of 35) sorted by relevance

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/drivers/scsi/qla2xxx/
Dqla_fw.h23 #define FO1_ENABLE_8016 BIT_0
32 #define PDO_FORCE_PLOGI BIT_0
455 #define BD_WRITE_DATA BIT_0
493 #define CF_WRITE_DATA BIT_0
535 #define TMF_WRITE_DATA BIT_0
617 #define SF_FCP_RSP_DMA BIT_0
909 #define TCF_CLEAR_ACA BIT_0
932 #define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */
1026 #define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */
1095 #define GPDX_DATA_INOUT (BIT_1|BIT_0)
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Dqla_def.h80 #define BIT_0 0x1 macro
164 #define IDC_DEVICE_STATE_CHANGE BIT_0
184 #define QLA83XX_IDC_RESET_DISABLED BIT_0
327 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
441 #define SRB_LOGIN_RETRIED BIT_0
486 #define SRB_FXDISC_REQ_DMA_VALID BIT_0
672 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
690 #define NVR_CLOCK BIT_0
945 #define MBX_DMA_IN BIT_0
958 #define MBX_DMA_IN BIT_0
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Dqla_target.h226 #define ATIO_EXEC_WRITE BIT_0
471 #define CTIO7_FLAGS_DATA_OUT BIT_0 /* data from initiator */
573 #define ABTS_PARAM_ABORT_SEQ BIT_0
611 #define ABTS_CONTR_FLG_TERM_EXCHG BIT_0
828 TRC_NEW_CMD = BIT_0,
954 #define QLA24XX_MGMT_SEND_NACK BIT_0
Dqla_nvme.h64 #define CF_WRITE_DATA BIT_0
Dqla_tmpl.h61 #define CAPTURE_FLAG_PHYS_ONLY BIT_0
Dqla_mbx.c228 if (mboxes & BIT_0) { in qla2x00_mailbox_command()
400 if (mboxes & BIT_0) { in qla2x00_mailbox_command()
568 if (mboxes & BIT_0) { in qla2x00_mailbox_command()
646 #define EXTENDED_BB_CREDITS BIT_0
650 uint16_t mb4 = BIT_0; in qla25xx_set_sfp_lr_dist()
660 uint16_t mb4 = BIT_0; in qla25xx_set_nvr_lr_dist()
779 ha->max_supported_speed = mcp->mb[2] & (BIT_0|BIT_1); in qla2x00_execute_fw()
786 (BIT_0 | BIT_1 | BIT_2); in qla2x00_execute_fw()
1811 mcp->mb[1] = BIT_0; in qla2x00_init_firmware()
2390 if (opt & BIT_0) in qla24xx_login_fabric()
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Dqla_init.c2198 if (RD_REG_DWORD(&reg->mailbox12) & BIT_0) { in qla2x00_initialize_adapter()
3778 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
3782 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
3792 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options()
3793 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
3798 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); in qla2x00_update_fw_options()
3800 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
3810 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options()
3811 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
3897 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0) in qla24xx_update_fw_options()
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Dqla_nx.h839 #define HINT_MBX_INT_PENDING BIT_0
848 #define ISRX_NX_RISC_INT BIT_0 /* RISC interrupt. */
Dqla_isr.c91 if (RD_REG_WORD(&reg->semaphore) & BIT_0) { in qla2100_intr_handler()
299 if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0)) in qla2x00_mbx_completion()
301 else if (mboxes & BIT_0) in qla2x00_mbx_completion()
1400 if (le16_to_cpu(mbx->mb1) & BIT_0) in qla2x00_mbx_iocb_entry()
2933 if (mboxes & BIT_0) in qla24xx_mbx_completion()
3115 for (cnt = 10000; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()
3128 for (cnt = 100; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()
Dqla_mid.c607 req->options |= BIT_0; in qla25xx_delete_req_que()
624 rsp->options |= BIT_0; in qla25xx_delete_rsp_que()
Dqla_sup.c40 while ((data & BIT_0) == 0) { in qla2x00_lock_nvram_access()
129 data |= BIT_0; in qla2x00_nvram_request()
1162 if ((flags & BIT_0) == 0) in qla2xxx_flash_npiv_conf()
1235 if (!(dword & BIT_0)) in qla24xx_protect_flash()
Dqla_iocb.c1741 #define QDSS_GOT_Q_SPACE BIT_0 in qla24xx_dif_start_scsi()
2063 #define QDSS_GOT_Q_SPACE BIT_0 in qla2xxx_dif_start_scsi_mq()
2391 opts = lio->u.logio.flags & SRB_LOGIN_COND_PLOGI ? BIT_0 : 0; in qla2x00_login_iocb()
2465 mbx->mb10 = cpu_to_le16(BIT_0); in qla2x00_adisc_iocb()
2467 mbx->mb1 = cpu_to_le16((sp->fcport->loop_id << 8) | BIT_0); in qla2x00_adisc_iocb()
/drivers/scsi/
Dqla1280.h17 #define BIT_0 0x1 macro
120 #define ISP_CFG0_1020 BIT_0 /* ISP1020 */
132 #define ISP_CFG1_SXP BIT_0 /* SXP register select */
134 #define ISP_RESET BIT_0 /* ISP soft reset */
146 #define NV_CLOCK BIT_0
160 #define CDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */
177 #define DDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */
203 #define BIOS_ENABLE BIT_0
565 #define RF_CONT BIT_0 /* Continuation. */
Dqla1280.c1124 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; in qla1280_set_target_parameters()
1198 (ha->bus_settings[bus].qtag_enables & (BIT_0 << target))) { in qla1280_slave_configure()
1691 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb); in qla1280_load_firmware_pio()
1763 BIT_1 | BIT_0, mb); in qla1280_load_firmware_dma()
1780 BIT_1 | BIT_0, mb); in qla1280_load_firmware_dma()
1825 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); in qla1280_start_firmware()
1835 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_start_firmware()
1902 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
1916 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
2090 flag = (BIT_0 << target); in qla1280_config_target()
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/drivers/net/ethernet/qlogic/qlcnic/
Dqlcnic_hw.h141 #define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1))
Dqlcnic_83xx_hw.h365 #define QLC_83XX_LINK_STATS(data) ((data) & BIT_0)
531 #define QLC_REGISTER_LB_IDC BIT_0
Dqlcnic_hdr.h196 #define BIT_0 0x1 macro
493 #define TA_CTL_START BIT_0
Dqlcnic_ctx.c1336 arg1 = (adapter->npars[index].phy_port & BIT_0); in qlcnic_config_switch_port()
1347 arg2 |= (BIT_0 | BIT_1); in qlcnic_config_switch_port()
1357 arg2 &= ~BIT_0; in qlcnic_config_switch_port()
1358 if (!(esw_cfg->offload_flags & BIT_0)) in qlcnic_config_switch_port()
Dqlcnic_hw.c819 #define QLCNIC_ENABLE_IPV4_LRO BIT_0
1033 if (offload_flags & BIT_0) { in qlcnic_process_flags()
Dqlcnic_minidump.c24 #define QLCNIC_DUMP_WCRB BIT_0
299 fw_dump->use_pex_dma = (hdr->capabilities & BIT_0) ? true : false; in qlcnic_82xx_cache_tmpl_hdr_values()
Dqlcnic_io.c363 #define QLCNIC_ENCAP_VXLAN_PKT BIT_0
494 if (*(skb->data) & BIT_0) { in qlcnic_tx_pkt()
495 flags |= BIT_0; in qlcnic_tx_pkt()
Dqlcnic_sriov_pf.c393 cmd.req.arg[1] |= BIT_0; in qlcnic_sriov_pf_cfg_eswitch()
1896 nic_info.bit_offsets = BIT_0; in qlcnic_sriov_set_vf_tx_rate()
/drivers/scsi/qla4xxx/
Dql4_fw.h55 #define HINT_MBX_INT_PENDING BIT_0
61 #define HSRX_RISC_MB_INT BIT_0 /* RISC to Host Mailbox interrupt */
65 #define ISRX_82XX_RISC_INT BIT_0 /* RISC interrupt. */
Dql4_def.h82 #define BIT_0 0x1 macro
Dql4_init.c294 if (!(le32_to_cpu(*cap_offset) & BIT_0)) { in qla4_80xx_is_minidump_dma_capable()

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