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Searched refs:BIT_2 (Results 1 – 21 of 21) sorted by relevance

/drivers/scsi/
Dqla1280.h19 #define BIT_2 0x4 macro
122 #define ISP_CFG0_1040 BIT_2 /* ISP1040 */
131 #define ISP_CFG1_BENAB BIT_2 /* Global Bus burst enable */
136 #define ISP_EN_RISC BIT_2 /* ISP enable RISC interrupts. */
141 #define RISC_INT BIT_2 /* RISC interrupt */
148 #define NV_DATA_OUT BIT_2
158 #define CDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */
175 #define DDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */
323 #define NV_START_BIT BIT_2
567 #define RF_BAD_HEADER BIT_2 /* Bad header. */
Dqla1280.c1124 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; in qla1280_set_target_parameters()
1691 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb); in qla1280_load_firmware_pio()
1762 err = qla1280_mailbox_command(ha, BIT_4 | BIT_3 | BIT_2 | in qla1280_load_firmware_dma()
1779 err = qla1280_mailbox_command(ha, BIT_4 | BIT_3 | BIT_2 | in qla1280_load_firmware_dma()
1902 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
1916 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
2210 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla1280_nvram_config()
2244 status |= qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_2 | in qla1280_nvram_config()
2251 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]); in qla1280_nvram_config()
2265 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb); in qla1280_nvram_config()
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/drivers/scsi/qla2xxx/
Dqla_fw.h491 #define CF_DATA_SEG_DESCR_ENABLE BIT_2
533 #define TMF_DSD_LIST_ENABLE BIT_2
907 #define TCF_CLEAR_TASK_SET BIT_2
1024 #define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */
1087 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)
1091 #define GPDX_LED_YELLOW_ON BIT_2
1290 #define CS_VF_SET_HOPS_OF_VPORTS BIT_2
1576 #define FSTATE_IS_DIAG_FW BIT_2
1592 #define VCO_DONT_RESET_UPDATE BIT_2
Dqla_def.h82 #define BIT_2 0x4 macro
166 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
329 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
443 #define SRB_LOGIN_SKIP_PRLI BIT_2
488 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2
688 #define NVR_DATA_OUT BIT_2
947 #define IOCTL_CMD BIT_2
960 #define IOCTL_CMD BIT_2
1259 #define MBX_2 BIT_2
1364 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
[all …]
Dqla_nvme.h62 #define CF_DATA_SEG_DESCR_ENABLE BIT_2
Dqla_init.c1105 mb[1] = BIT_2 | BIT_3; in qla24xx_async_gnl()
3644 (ha->fw_attributes & BIT_2)) { in qla2x00_setup_chip()
3774 if (ha->fw_seriallink_options[3] & BIT_2) { in qla2x00_update_fw_options()
3778 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
3782 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
3800 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4516 nv->firmware_options[0] = BIT_2 | BIT_1; in qla2x00_nvram_config()
4523 nv->firmware_options[0] = BIT_2 | BIT_1; in qla2x00_nvram_config()
4550 nv->host_p[1] = BIT_2; in qla2x00_nvram_config()
4571 nv->firmware_options[0] |= BIT_2; in qla2x00_nvram_config()
[all …]
Dqla_target.h469 #define CTIO7_FLAGS_DSD_PTR BIT_2
830 TRC_DO_WORK_ERR = BIT_2,
Dqla_mbx.c786 (BIT_0 | BIT_1 | BIT_2); in qla2x00_execute_fw()
5503 mcp->mb[2] = BIT_2; in qla24xx_set_fcp_prio()
6094 if (subcode & BIT_2) { in qla83xx_access_control()
6102 if (!(subcode & (BIT_2 | BIT_5))) in qla83xx_access_control()
/drivers/net/ethernet/qlogic/qlcnic/
Dqlcnic_ctx.c1343 arg1 &= ~(BIT_2 | BIT_3); in qlcnic_config_switch_port()
1349 arg2 |= (BIT_2 | BIT_3); in qlcnic_config_switch_port()
1359 arg2 &= ~(BIT_1 | BIT_2 | BIT_3); in qlcnic_config_switch_port()
1361 arg2 &= ~BIT_2; in qlcnic_config_switch_port()
1362 if (!(esw_cfg->offload_flags & BIT_2)) in qlcnic_config_switch_port()
1367 arg1 |= (BIT_2 | BIT_5); in qlcnic_config_switch_port()
Dqlcnic_hdr.h198 #define BIT_2 0x4 macro
495 #define TA_CTL_WRITE BIT_2
Dqlcnic.h924 #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2
1322 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
Dqlcnic_83xx_hw.c751 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8); in qlcnic_83xx_enable_mbx_interrupt()
753 val = BIT_2; in qlcnic_83xx_enable_mbx_interrupt()
2019 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0); in qlcnic_83xx_config_hw_lro()
3542 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16); in qlcnic_83xx_get_stats()
Dqlcnic_dcb.c552 if (mbx_out & BIT_2) in qlcnic_83xx_dcb_get_hw_capability()
Dqlcnic_hw.c1043 if (!(offload_flags & BIT_2)) in qlcnic_process_flags()
Dqlcnic_minidump.c26 #define QLCNIC_DUMP_ANDCRB BIT_2
Dqlcnic_83xx_init.c1024 #define QLC_83XX_MATCH_ENCAP_ID BIT_2
Dqlcnic_sriov_common.c383 if (status & BIT_2) in qlcnic_sriov_get_vf_vport_info()
Dqlcnic_io.c365 #define QLCNIC_ENCAP_INNER_L3_IP6 BIT_2
Dqlcnic_main.c1525 esw_cfg.offload_flags |= (BIT_1 | BIT_2); in qlcnic_set_default_offload_settings()
/drivers/scsi/qla4xxx/
Dql4_def.h84 #define BIT_2 0x4 macro
Dql4_os.c3522 conn->tcp_timer_scale |= BIT_2; in qla4xxx_copy_from_fwddb_param()
3650 SET_BITVAL(conn->tcp_timer_scale & BIT_2, options, BIT_3); in qla4xxx_copy_to_fwddb_param()
3651 SET_BITVAL(conn->tcp_timer_scale & BIT_1, options, BIT_2); in qla4xxx_copy_to_fwddb_param()
3759 conn->tcp_timer_scale |= BIT_2; in qla4xxx_copy_to_sess_conn_params()