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Searched refs:DUMPREG (Results 1 – 15 of 15) sorted by relevance

/drivers/media/platform/ti-vpe/
Dsc.c25 #define DUMPREG(r) dev_dbg(dev, "%-35s %08x\n", #r, \ in sc_dump_regs() macro
30 DUMPREG(SC0); in sc_dump_regs()
31 DUMPREG(SC1); in sc_dump_regs()
32 DUMPREG(SC2); in sc_dump_regs()
33 DUMPREG(SC3); in sc_dump_regs()
34 DUMPREG(SC4); in sc_dump_regs()
35 DUMPREG(SC5); in sc_dump_regs()
36 DUMPREG(SC6); in sc_dump_regs()
37 DUMPREG(SC8); in sc_dump_regs()
38 DUMPREG(SC9); in sc_dump_regs()
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Dcsc.c94 #define DUMPREG(r) dev_dbg(dev, "%-35s %08x\n", #r, \ in csc_dump_regs() macro
99 DUMPREG(CSC00); in csc_dump_regs()
100 DUMPREG(CSC01); in csc_dump_regs()
101 DUMPREG(CSC02); in csc_dump_regs()
102 DUMPREG(CSC03); in csc_dump_regs()
103 DUMPREG(CSC04); in csc_dump_regs()
104 DUMPREG(CSC05); in csc_dump_regs()
106 #undef DUMPREG in csc_dump_regs()
Dvpdma.c306 #define DUMPREG(r) dev_dbg(dev, "%-35s %08x\n", #r, read_reg(vpdma, VPDMA_##r)) in vpdma_dump_regs() macro
310 DUMPREG(PID); in vpdma_dump_regs()
311 DUMPREG(LIST_ADDR); in vpdma_dump_regs()
312 DUMPREG(LIST_ATTR); in vpdma_dump_regs()
313 DUMPREG(LIST_STAT_SYNC); in vpdma_dump_regs()
314 DUMPREG(BG_RGB); in vpdma_dump_regs()
315 DUMPREG(BG_YUV); in vpdma_dump_regs()
316 DUMPREG(SETUP); in vpdma_dump_regs()
317 DUMPREG(MAX_SIZE1); in vpdma_dump_regs()
318 DUMPREG(MAX_SIZE2); in vpdma_dump_regs()
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Dvpe.c949 #define DUMPREG(r) vpe_dbg(dev, "%-35s %08x\n", #r, read_reg(dev, VPE_##r)) in vpe_dump_regs() macro
953 DUMPREG(PID); in vpe_dump_regs()
954 DUMPREG(SYSCONFIG); in vpe_dump_regs()
955 DUMPREG(INT0_STATUS0_RAW); in vpe_dump_regs()
956 DUMPREG(INT0_STATUS0); in vpe_dump_regs()
957 DUMPREG(INT0_ENABLE0); in vpe_dump_regs()
958 DUMPREG(INT0_STATUS1_RAW); in vpe_dump_regs()
959 DUMPREG(INT0_STATUS1); in vpe_dump_regs()
960 DUMPREG(INT0_ENABLE1); in vpe_dump_regs()
961 DUMPREG(CLK_ENABLE); in vpe_dump_regs()
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/drivers/video/fbdev/omap2/omapfb/dss/
Dvenc.c648 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r)) in venc_dump_regs() macro
653 DUMPREG(VENC_F_CONTROL); in venc_dump_regs()
654 DUMPREG(VENC_VIDOUT_CTRL); in venc_dump_regs()
655 DUMPREG(VENC_SYNC_CTRL); in venc_dump_regs()
656 DUMPREG(VENC_LLEN); in venc_dump_regs()
657 DUMPREG(VENC_FLENS); in venc_dump_regs()
658 DUMPREG(VENC_HFLTR_CTRL); in venc_dump_regs()
659 DUMPREG(VENC_CC_CARR_WSS_CARR); in venc_dump_regs()
660 DUMPREG(VENC_C_PHASE); in venc_dump_regs()
661 DUMPREG(VENC_GAIN_U); in venc_dump_regs()
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Dhdmi_wp.c23 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump() macro
25 DUMPREG(HDMI_WP_REVISION); in hdmi_wp_dump()
26 DUMPREG(HDMI_WP_SYSCONFIG); in hdmi_wp_dump()
27 DUMPREG(HDMI_WP_IRQSTATUS_RAW); in hdmi_wp_dump()
28 DUMPREG(HDMI_WP_IRQSTATUS); in hdmi_wp_dump()
29 DUMPREG(HDMI_WP_IRQENABLE_SET); in hdmi_wp_dump()
30 DUMPREG(HDMI_WP_IRQENABLE_CLR); in hdmi_wp_dump()
31 DUMPREG(HDMI_WP_IRQWAKEEN); in hdmi_wp_dump()
32 DUMPREG(HDMI_WP_PWR_CTRL); in hdmi_wp_dump()
33 DUMPREG(HDMI_WP_DEBOUNCE); in hdmi_wp_dump()
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Ddispc.c3511 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r)) in dispc_dump_regs() macro
3517 DUMPREG(DISPC_REVISION); in dispc_dump_regs()
3518 DUMPREG(DISPC_SYSCONFIG); in dispc_dump_regs()
3519 DUMPREG(DISPC_SYSSTATUS); in dispc_dump_regs()
3520 DUMPREG(DISPC_IRQSTATUS); in dispc_dump_regs()
3521 DUMPREG(DISPC_IRQENABLE); in dispc_dump_regs()
3522 DUMPREG(DISPC_CONTROL); in dispc_dump_regs()
3523 DUMPREG(DISPC_CONFIG); in dispc_dump_regs()
3524 DUMPREG(DISPC_CAPABLE); in dispc_dump_regs()
3525 DUMPREG(DISPC_LINE_STATUS); in dispc_dump_regs()
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Ddsi.c1641 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r)) in dsi_dump_dsidev_regs() macro
1647 DUMPREG(DSI_REVISION); in dsi_dump_dsidev_regs()
1648 DUMPREG(DSI_SYSCONFIG); in dsi_dump_dsidev_regs()
1649 DUMPREG(DSI_SYSSTATUS); in dsi_dump_dsidev_regs()
1650 DUMPREG(DSI_IRQSTATUS); in dsi_dump_dsidev_regs()
1651 DUMPREG(DSI_IRQENABLE); in dsi_dump_dsidev_regs()
1652 DUMPREG(DSI_CTRL); in dsi_dump_dsidev_regs()
1653 DUMPREG(DSI_COMPLEXIO_CFG1); in dsi_dump_dsidev_regs()
1654 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); in dsi_dump_dsidev_regs()
1655 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); in dsi_dump_dsidev_regs()
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Ddss.c374 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) in dss_dump_regs() macro
379 DUMPREG(DSS_REVISION); in dss_dump_regs()
380 DUMPREG(DSS_SYSCONFIG); in dss_dump_regs()
381 DUMPREG(DSS_SYSSTATUS); in dss_dump_regs()
382 DUMPREG(DSS_CONTROL); in dss_dump_regs()
386 DUMPREG(DSS_SDI_CONTROL); in dss_dump_regs()
387 DUMPREG(DSS_PLL_CONTROL); in dss_dump_regs()
388 DUMPREG(DSS_SDI_STATUS); in dss_dump_regs()
392 #undef DUMPREG in dss_dump_regs()
/drivers/gpu/drm/omapdrm/dss/
Dvenc.c603 #define DUMPREG(venc, r) \ in venc_dump_regs() macro
609 DUMPREG(venc, VENC_F_CONTROL); in venc_dump_regs()
610 DUMPREG(venc, VENC_VIDOUT_CTRL); in venc_dump_regs()
611 DUMPREG(venc, VENC_SYNC_CTRL); in venc_dump_regs()
612 DUMPREG(venc, VENC_LLEN); in venc_dump_regs()
613 DUMPREG(venc, VENC_FLENS); in venc_dump_regs()
614 DUMPREG(venc, VENC_HFLTR_CTRL); in venc_dump_regs()
615 DUMPREG(venc, VENC_CC_CARR_WSS_CARR); in venc_dump_regs()
616 DUMPREG(venc, VENC_C_PHASE); in venc_dump_regs()
617 DUMPREG(venc, VENC_GAIN_U); in venc_dump_regs()
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Dhdmi_wp.c22 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump() macro
24 DUMPREG(HDMI_WP_REVISION); in hdmi_wp_dump()
25 DUMPREG(HDMI_WP_SYSCONFIG); in hdmi_wp_dump()
26 DUMPREG(HDMI_WP_IRQSTATUS_RAW); in hdmi_wp_dump()
27 DUMPREG(HDMI_WP_IRQSTATUS); in hdmi_wp_dump()
28 DUMPREG(HDMI_WP_IRQENABLE_SET); in hdmi_wp_dump()
29 DUMPREG(HDMI_WP_IRQENABLE_CLR); in hdmi_wp_dump()
30 DUMPREG(HDMI_WP_IRQWAKEEN); in hdmi_wp_dump()
31 DUMPREG(HDMI_WP_PWR_CTRL); in hdmi_wp_dump()
32 DUMPREG(HDMI_WP_DEBOUNCE); in hdmi_wp_dump()
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Ddispc.c3470 #define DUMPREG(dispc, r) \ in dispc_dump_regs() macro
3477 DUMPREG(dispc, DISPC_REVISION); in dispc_dump_regs()
3478 DUMPREG(dispc, DISPC_SYSCONFIG); in dispc_dump_regs()
3479 DUMPREG(dispc, DISPC_SYSSTATUS); in dispc_dump_regs()
3480 DUMPREG(dispc, DISPC_IRQSTATUS); in dispc_dump_regs()
3481 DUMPREG(dispc, DISPC_IRQENABLE); in dispc_dump_regs()
3482 DUMPREG(dispc, DISPC_CONTROL); in dispc_dump_regs()
3483 DUMPREG(dispc, DISPC_CONFIG); in dispc_dump_regs()
3484 DUMPREG(dispc, DISPC_CAPABLE); in dispc_dump_regs()
3485 DUMPREG(dispc, DISPC_LINE_STATUS); in dispc_dump_regs()
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Ddsi.c1542 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsi, r)) in dsi_dump_dsi_regs() macro
1543 DUMPREG(DSI_REVISION); in dsi_dump_dsi_regs()
1544 DUMPREG(DSI_SYSCONFIG); in dsi_dump_dsi_regs()
1545 DUMPREG(DSI_SYSSTATUS); in dsi_dump_dsi_regs()
1546 DUMPREG(DSI_IRQSTATUS); in dsi_dump_dsi_regs()
1547 DUMPREG(DSI_IRQENABLE); in dsi_dump_dsi_regs()
1548 DUMPREG(DSI_CTRL); in dsi_dump_dsi_regs()
1549 DUMPREG(DSI_COMPLEXIO_CFG1); in dsi_dump_dsi_regs()
1550 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); in dsi_dump_dsi_regs()
1551 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); in dsi_dump_dsi_regs()
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Ddss.c359 #define DUMPREG(dss, r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(dss, r)) in dss_dump_regs() macro
364 DUMPREG(dss, DSS_REVISION); in dss_dump_regs()
365 DUMPREG(dss, DSS_SYSCONFIG); in dss_dump_regs()
366 DUMPREG(dss, DSS_SYSSTATUS); in dss_dump_regs()
367 DUMPREG(dss, DSS_CONTROL); in dss_dump_regs()
370 DUMPREG(dss, DSS_SDI_CONTROL); in dss_dump_regs()
371 DUMPREG(dss, DSS_PLL_CONTROL); in dss_dump_regs()
372 DUMPREG(dss, DSS_SDI_STATUS); in dss_dump_regs()
376 #undef DUMPREG in dss_dump_regs()
/drivers/gpu/drm/exynos/
Dexynos_mixer.c223 #define DUMPREG(reg_id) \ in mixer_regs_dump() macro
229 DUMPREG(MXR_STATUS); in mixer_regs_dump()
230 DUMPREG(MXR_CFG); in mixer_regs_dump()
231 DUMPREG(MXR_INT_EN); in mixer_regs_dump()
232 DUMPREG(MXR_INT_STATUS); in mixer_regs_dump()
234 DUMPREG(MXR_LAYER_CFG); in mixer_regs_dump()
235 DUMPREG(MXR_VIDEO_CFG); in mixer_regs_dump()
237 DUMPREG(MXR_GRAPHIC0_CFG); in mixer_regs_dump()
238 DUMPREG(MXR_GRAPHIC0_BASE); in mixer_regs_dump()
239 DUMPREG(MXR_GRAPHIC0_SPAN); in mixer_regs_dump()
[all …]