1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * VPDMA helper library
4 *
5 * Copyright (c) 2013 Texas Instruments Inc.
6 *
7 * David Griego, <dagriego@biglakesoftware.com>
8 * Dale Farnsworth, <dale@farnsworth.org>
9 * Archit Taneja, <archit@ti.com>
10 */
11
12 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/err.h>
15 #include <linux/firmware.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22
23 #include "vpdma.h"
24 #include "vpdma_priv.h"
25
26 #define VPDMA_FIRMWARE "vpdma-1b8.bin"
27
28 const struct vpdma_data_format vpdma_yuv_fmts[] = {
29 [VPDMA_DATA_FMT_Y444] = {
30 .type = VPDMA_DATA_FMT_TYPE_YUV,
31 .data_type = DATA_TYPE_Y444,
32 .depth = 8,
33 },
34 [VPDMA_DATA_FMT_Y422] = {
35 .type = VPDMA_DATA_FMT_TYPE_YUV,
36 .data_type = DATA_TYPE_Y422,
37 .depth = 8,
38 },
39 [VPDMA_DATA_FMT_Y420] = {
40 .type = VPDMA_DATA_FMT_TYPE_YUV,
41 .data_type = DATA_TYPE_Y420,
42 .depth = 8,
43 },
44 [VPDMA_DATA_FMT_C444] = {
45 .type = VPDMA_DATA_FMT_TYPE_YUV,
46 .data_type = DATA_TYPE_C444,
47 .depth = 8,
48 },
49 [VPDMA_DATA_FMT_C422] = {
50 .type = VPDMA_DATA_FMT_TYPE_YUV,
51 .data_type = DATA_TYPE_C422,
52 .depth = 8,
53 },
54 [VPDMA_DATA_FMT_C420] = {
55 .type = VPDMA_DATA_FMT_TYPE_YUV,
56 .data_type = DATA_TYPE_C420,
57 .depth = 4,
58 },
59 [VPDMA_DATA_FMT_YCR422] = {
60 .type = VPDMA_DATA_FMT_TYPE_YUV,
61 .data_type = DATA_TYPE_YCR422,
62 .depth = 16,
63 },
64 [VPDMA_DATA_FMT_YC444] = {
65 .type = VPDMA_DATA_FMT_TYPE_YUV,
66 .data_type = DATA_TYPE_YC444,
67 .depth = 24,
68 },
69 [VPDMA_DATA_FMT_CRY422] = {
70 .type = VPDMA_DATA_FMT_TYPE_YUV,
71 .data_type = DATA_TYPE_CRY422,
72 .depth = 16,
73 },
74 [VPDMA_DATA_FMT_CBY422] = {
75 .type = VPDMA_DATA_FMT_TYPE_YUV,
76 .data_type = DATA_TYPE_CBY422,
77 .depth = 16,
78 },
79 [VPDMA_DATA_FMT_YCB422] = {
80 .type = VPDMA_DATA_FMT_TYPE_YUV,
81 .data_type = DATA_TYPE_YCB422,
82 .depth = 16,
83 },
84 };
85 EXPORT_SYMBOL(vpdma_yuv_fmts);
86
87 const struct vpdma_data_format vpdma_rgb_fmts[] = {
88 [VPDMA_DATA_FMT_RGB565] = {
89 .type = VPDMA_DATA_FMT_TYPE_RGB,
90 .data_type = DATA_TYPE_RGB16_565,
91 .depth = 16,
92 },
93 [VPDMA_DATA_FMT_ARGB16_1555] = {
94 .type = VPDMA_DATA_FMT_TYPE_RGB,
95 .data_type = DATA_TYPE_ARGB_1555,
96 .depth = 16,
97 },
98 [VPDMA_DATA_FMT_ARGB16] = {
99 .type = VPDMA_DATA_FMT_TYPE_RGB,
100 .data_type = DATA_TYPE_ARGB_4444,
101 .depth = 16,
102 },
103 [VPDMA_DATA_FMT_RGBA16_5551] = {
104 .type = VPDMA_DATA_FMT_TYPE_RGB,
105 .data_type = DATA_TYPE_RGBA_5551,
106 .depth = 16,
107 },
108 [VPDMA_DATA_FMT_RGBA16] = {
109 .type = VPDMA_DATA_FMT_TYPE_RGB,
110 .data_type = DATA_TYPE_RGBA_4444,
111 .depth = 16,
112 },
113 [VPDMA_DATA_FMT_ARGB24] = {
114 .type = VPDMA_DATA_FMT_TYPE_RGB,
115 .data_type = DATA_TYPE_ARGB24_6666,
116 .depth = 24,
117 },
118 [VPDMA_DATA_FMT_RGB24] = {
119 .type = VPDMA_DATA_FMT_TYPE_RGB,
120 .data_type = DATA_TYPE_RGB24_888,
121 .depth = 24,
122 },
123 [VPDMA_DATA_FMT_ARGB32] = {
124 .type = VPDMA_DATA_FMT_TYPE_RGB,
125 .data_type = DATA_TYPE_ARGB32_8888,
126 .depth = 32,
127 },
128 [VPDMA_DATA_FMT_RGBA24] = {
129 .type = VPDMA_DATA_FMT_TYPE_RGB,
130 .data_type = DATA_TYPE_RGBA24_6666,
131 .depth = 24,
132 },
133 [VPDMA_DATA_FMT_RGBA32] = {
134 .type = VPDMA_DATA_FMT_TYPE_RGB,
135 .data_type = DATA_TYPE_RGBA32_8888,
136 .depth = 32,
137 },
138 [VPDMA_DATA_FMT_BGR565] = {
139 .type = VPDMA_DATA_FMT_TYPE_RGB,
140 .data_type = DATA_TYPE_BGR16_565,
141 .depth = 16,
142 },
143 [VPDMA_DATA_FMT_ABGR16_1555] = {
144 .type = VPDMA_DATA_FMT_TYPE_RGB,
145 .data_type = DATA_TYPE_ABGR_1555,
146 .depth = 16,
147 },
148 [VPDMA_DATA_FMT_ABGR16] = {
149 .type = VPDMA_DATA_FMT_TYPE_RGB,
150 .data_type = DATA_TYPE_ABGR_4444,
151 .depth = 16,
152 },
153 [VPDMA_DATA_FMT_BGRA16_5551] = {
154 .type = VPDMA_DATA_FMT_TYPE_RGB,
155 .data_type = DATA_TYPE_BGRA_5551,
156 .depth = 16,
157 },
158 [VPDMA_DATA_FMT_BGRA16] = {
159 .type = VPDMA_DATA_FMT_TYPE_RGB,
160 .data_type = DATA_TYPE_BGRA_4444,
161 .depth = 16,
162 },
163 [VPDMA_DATA_FMT_ABGR24] = {
164 .type = VPDMA_DATA_FMT_TYPE_RGB,
165 .data_type = DATA_TYPE_ABGR24_6666,
166 .depth = 24,
167 },
168 [VPDMA_DATA_FMT_BGR24] = {
169 .type = VPDMA_DATA_FMT_TYPE_RGB,
170 .data_type = DATA_TYPE_BGR24_888,
171 .depth = 24,
172 },
173 [VPDMA_DATA_FMT_ABGR32] = {
174 .type = VPDMA_DATA_FMT_TYPE_RGB,
175 .data_type = DATA_TYPE_ABGR32_8888,
176 .depth = 32,
177 },
178 [VPDMA_DATA_FMT_BGRA24] = {
179 .type = VPDMA_DATA_FMT_TYPE_RGB,
180 .data_type = DATA_TYPE_BGRA24_6666,
181 .depth = 24,
182 },
183 [VPDMA_DATA_FMT_BGRA32] = {
184 .type = VPDMA_DATA_FMT_TYPE_RGB,
185 .data_type = DATA_TYPE_BGRA32_8888,
186 .depth = 32,
187 },
188 };
189 EXPORT_SYMBOL(vpdma_rgb_fmts);
190
191 /*
192 * To handle RAW format we are re-using the CBY422
193 * vpdma data type so that we use the vpdma to re-order
194 * the incoming bytes, as the parser assumes that the
195 * first byte presented on the bus is the MSB of a 2
196 * bytes value.
197 * RAW8 handles from 1 to 8 bits
198 * RAW16 handles from 9 to 16 bits
199 */
200 const struct vpdma_data_format vpdma_raw_fmts[] = {
201 [VPDMA_DATA_FMT_RAW8] = {
202 .type = VPDMA_DATA_FMT_TYPE_YUV,
203 .data_type = DATA_TYPE_CBY422,
204 .depth = 8,
205 },
206 [VPDMA_DATA_FMT_RAW16] = {
207 .type = VPDMA_DATA_FMT_TYPE_YUV,
208 .data_type = DATA_TYPE_CBY422,
209 .depth = 16,
210 },
211 };
212 EXPORT_SYMBOL(vpdma_raw_fmts);
213
214 const struct vpdma_data_format vpdma_misc_fmts[] = {
215 [VPDMA_DATA_FMT_MV] = {
216 .type = VPDMA_DATA_FMT_TYPE_MISC,
217 .data_type = DATA_TYPE_MV,
218 .depth = 4,
219 },
220 };
221 EXPORT_SYMBOL(vpdma_misc_fmts);
222
223 struct vpdma_channel_info {
224 int num; /* VPDMA channel number */
225 int cstat_offset; /* client CSTAT register offset */
226 };
227
228 static const struct vpdma_channel_info chan_info[] = {
229 [VPE_CHAN_LUMA1_IN] = {
230 .num = VPE_CHAN_NUM_LUMA1_IN,
231 .cstat_offset = VPDMA_DEI_LUMA1_CSTAT,
232 },
233 [VPE_CHAN_CHROMA1_IN] = {
234 .num = VPE_CHAN_NUM_CHROMA1_IN,
235 .cstat_offset = VPDMA_DEI_CHROMA1_CSTAT,
236 },
237 [VPE_CHAN_LUMA2_IN] = {
238 .num = VPE_CHAN_NUM_LUMA2_IN,
239 .cstat_offset = VPDMA_DEI_LUMA2_CSTAT,
240 },
241 [VPE_CHAN_CHROMA2_IN] = {
242 .num = VPE_CHAN_NUM_CHROMA2_IN,
243 .cstat_offset = VPDMA_DEI_CHROMA2_CSTAT,
244 },
245 [VPE_CHAN_LUMA3_IN] = {
246 .num = VPE_CHAN_NUM_LUMA3_IN,
247 .cstat_offset = VPDMA_DEI_LUMA3_CSTAT,
248 },
249 [VPE_CHAN_CHROMA3_IN] = {
250 .num = VPE_CHAN_NUM_CHROMA3_IN,
251 .cstat_offset = VPDMA_DEI_CHROMA3_CSTAT,
252 },
253 [VPE_CHAN_MV_IN] = {
254 .num = VPE_CHAN_NUM_MV_IN,
255 .cstat_offset = VPDMA_DEI_MV_IN_CSTAT,
256 },
257 [VPE_CHAN_MV_OUT] = {
258 .num = VPE_CHAN_NUM_MV_OUT,
259 .cstat_offset = VPDMA_DEI_MV_OUT_CSTAT,
260 },
261 [VPE_CHAN_LUMA_OUT] = {
262 .num = VPE_CHAN_NUM_LUMA_OUT,
263 .cstat_offset = VPDMA_VIP_UP_Y_CSTAT,
264 },
265 [VPE_CHAN_CHROMA_OUT] = {
266 .num = VPE_CHAN_NUM_CHROMA_OUT,
267 .cstat_offset = VPDMA_VIP_UP_UV_CSTAT,
268 },
269 [VPE_CHAN_RGB_OUT] = {
270 .num = VPE_CHAN_NUM_RGB_OUT,
271 .cstat_offset = VPDMA_VIP_UP_Y_CSTAT,
272 },
273 };
274
read_reg(struct vpdma_data * vpdma,int offset)275 static u32 read_reg(struct vpdma_data *vpdma, int offset)
276 {
277 return ioread32(vpdma->base + offset);
278 }
279
write_reg(struct vpdma_data * vpdma,int offset,u32 value)280 static void write_reg(struct vpdma_data *vpdma, int offset, u32 value)
281 {
282 iowrite32(value, vpdma->base + offset);
283 }
284
read_field_reg(struct vpdma_data * vpdma,int offset,u32 mask,int shift)285 static int read_field_reg(struct vpdma_data *vpdma, int offset,
286 u32 mask, int shift)
287 {
288 return (read_reg(vpdma, offset) & (mask << shift)) >> shift;
289 }
290
write_field_reg(struct vpdma_data * vpdma,int offset,u32 field,u32 mask,int shift)291 static void write_field_reg(struct vpdma_data *vpdma, int offset, u32 field,
292 u32 mask, int shift)
293 {
294 u32 val = read_reg(vpdma, offset);
295
296 val &= ~(mask << shift);
297 val |= (field & mask) << shift;
298
299 write_reg(vpdma, offset, val);
300 }
301
vpdma_dump_regs(struct vpdma_data * vpdma)302 void vpdma_dump_regs(struct vpdma_data *vpdma)
303 {
304 struct device *dev = &vpdma->pdev->dev;
305
306 #define DUMPREG(r) dev_dbg(dev, "%-35s %08x\n", #r, read_reg(vpdma, VPDMA_##r))
307
308 dev_dbg(dev, "VPDMA Registers:\n");
309
310 DUMPREG(PID);
311 DUMPREG(LIST_ADDR);
312 DUMPREG(LIST_ATTR);
313 DUMPREG(LIST_STAT_SYNC);
314 DUMPREG(BG_RGB);
315 DUMPREG(BG_YUV);
316 DUMPREG(SETUP);
317 DUMPREG(MAX_SIZE1);
318 DUMPREG(MAX_SIZE2);
319 DUMPREG(MAX_SIZE3);
320
321 /*
322 * dumping registers of only group0 and group3, because VPE channels
323 * lie within group0 and group3 registers
324 */
325 DUMPREG(INT_CHAN_STAT(0));
326 DUMPREG(INT_CHAN_MASK(0));
327 DUMPREG(INT_CHAN_STAT(3));
328 DUMPREG(INT_CHAN_MASK(3));
329 DUMPREG(INT_CLIENT0_STAT);
330 DUMPREG(INT_CLIENT0_MASK);
331 DUMPREG(INT_CLIENT1_STAT);
332 DUMPREG(INT_CLIENT1_MASK);
333 DUMPREG(INT_LIST0_STAT);
334 DUMPREG(INT_LIST0_MASK);
335
336 /*
337 * these are registers specific to VPE clients, we can make this
338 * function dump client registers specific to VPE or VIP based on
339 * who is using it
340 */
341 DUMPREG(DEI_CHROMA1_CSTAT);
342 DUMPREG(DEI_LUMA1_CSTAT);
343 DUMPREG(DEI_CHROMA2_CSTAT);
344 DUMPREG(DEI_LUMA2_CSTAT);
345 DUMPREG(DEI_CHROMA3_CSTAT);
346 DUMPREG(DEI_LUMA3_CSTAT);
347 DUMPREG(DEI_MV_IN_CSTAT);
348 DUMPREG(DEI_MV_OUT_CSTAT);
349 DUMPREG(VIP_UP_Y_CSTAT);
350 DUMPREG(VIP_UP_UV_CSTAT);
351 DUMPREG(VPI_CTL_CSTAT);
352 }
353 EXPORT_SYMBOL(vpdma_dump_regs);
354
355 /*
356 * Allocate a DMA buffer
357 */
vpdma_alloc_desc_buf(struct vpdma_buf * buf,size_t size)358 int vpdma_alloc_desc_buf(struct vpdma_buf *buf, size_t size)
359 {
360 buf->size = size;
361 buf->mapped = false;
362 buf->addr = kzalloc(size, GFP_KERNEL);
363 if (!buf->addr)
364 return -ENOMEM;
365
366 WARN_ON(((unsigned long)buf->addr & VPDMA_DESC_ALIGN) != 0);
367
368 return 0;
369 }
370 EXPORT_SYMBOL(vpdma_alloc_desc_buf);
371
vpdma_free_desc_buf(struct vpdma_buf * buf)372 void vpdma_free_desc_buf(struct vpdma_buf *buf)
373 {
374 WARN_ON(buf->mapped);
375 kfree(buf->addr);
376 buf->addr = NULL;
377 buf->size = 0;
378 }
379 EXPORT_SYMBOL(vpdma_free_desc_buf);
380
381 /*
382 * map descriptor/payload DMA buffer, enabling DMA access
383 */
vpdma_map_desc_buf(struct vpdma_data * vpdma,struct vpdma_buf * buf)384 int vpdma_map_desc_buf(struct vpdma_data *vpdma, struct vpdma_buf *buf)
385 {
386 struct device *dev = &vpdma->pdev->dev;
387
388 WARN_ON(buf->mapped);
389 buf->dma_addr = dma_map_single(dev, buf->addr, buf->size,
390 DMA_BIDIRECTIONAL);
391 if (dma_mapping_error(dev, buf->dma_addr)) {
392 dev_err(dev, "failed to map buffer\n");
393 return -EINVAL;
394 }
395
396 buf->mapped = true;
397
398 return 0;
399 }
400 EXPORT_SYMBOL(vpdma_map_desc_buf);
401
402 /*
403 * unmap descriptor/payload DMA buffer, disabling DMA access and
404 * allowing the main processor to access the data
405 */
vpdma_unmap_desc_buf(struct vpdma_data * vpdma,struct vpdma_buf * buf)406 void vpdma_unmap_desc_buf(struct vpdma_data *vpdma, struct vpdma_buf *buf)
407 {
408 struct device *dev = &vpdma->pdev->dev;
409
410 if (buf->mapped)
411 dma_unmap_single(dev, buf->dma_addr, buf->size,
412 DMA_BIDIRECTIONAL);
413
414 buf->mapped = false;
415 }
416 EXPORT_SYMBOL(vpdma_unmap_desc_buf);
417
418 /*
419 * Cleanup all pending descriptors of a list
420 * First, stop the current list being processed.
421 * If the VPDMA was busy, this step makes vpdma to accept post lists.
422 * To cleanup the internal FSM, post abort list descriptor for all the
423 * channels from @channels array of size @size.
424 */
vpdma_list_cleanup(struct vpdma_data * vpdma,int list_num,int * channels,int size)425 int vpdma_list_cleanup(struct vpdma_data *vpdma, int list_num,
426 int *channels, int size)
427 {
428 struct vpdma_desc_list abort_list;
429 int i, ret, timeout = 500;
430
431 write_reg(vpdma, VPDMA_LIST_ATTR,
432 (list_num << VPDMA_LIST_NUM_SHFT) |
433 (1 << VPDMA_LIST_STOP_SHFT));
434
435 if (size <= 0 || !channels)
436 return 0;
437
438 ret = vpdma_create_desc_list(&abort_list,
439 size * sizeof(struct vpdma_dtd), VPDMA_LIST_TYPE_NORMAL);
440 if (ret)
441 return ret;
442
443 for (i = 0; i < size; i++)
444 vpdma_add_abort_channel_ctd(&abort_list, channels[i]);
445
446 ret = vpdma_map_desc_buf(vpdma, &abort_list.buf);
447 if (ret)
448 goto free_desc;
449 ret = vpdma_submit_descs(vpdma, &abort_list, list_num);
450 if (ret)
451 goto unmap_desc;
452
453 while (vpdma_list_busy(vpdma, list_num) && --timeout)
454 ;
455
456 if (timeout == 0) {
457 dev_err(&vpdma->pdev->dev, "Timed out cleaning up VPDMA list\n");
458 ret = -EBUSY;
459 }
460
461 unmap_desc:
462 vpdma_unmap_desc_buf(vpdma, &abort_list.buf);
463 free_desc:
464 vpdma_free_desc_buf(&abort_list.buf);
465
466 return ret;
467 }
468 EXPORT_SYMBOL(vpdma_list_cleanup);
469
470 /*
471 * create a descriptor list, the user of this list will append configuration,
472 * control and data descriptors to this list, this list will be submitted to
473 * VPDMA. VPDMA's list parser will go through each descriptor and perform the
474 * required DMA operations
475 */
vpdma_create_desc_list(struct vpdma_desc_list * list,size_t size,int type)476 int vpdma_create_desc_list(struct vpdma_desc_list *list, size_t size, int type)
477 {
478 int r;
479
480 r = vpdma_alloc_desc_buf(&list->buf, size);
481 if (r)
482 return r;
483
484 list->next = list->buf.addr;
485
486 list->type = type;
487
488 return 0;
489 }
490 EXPORT_SYMBOL(vpdma_create_desc_list);
491
492 /*
493 * once a descriptor list is parsed by VPDMA, we reset the list by emptying it,
494 * to allow new descriptors to be added to the list.
495 */
vpdma_reset_desc_list(struct vpdma_desc_list * list)496 void vpdma_reset_desc_list(struct vpdma_desc_list *list)
497 {
498 list->next = list->buf.addr;
499 }
500 EXPORT_SYMBOL(vpdma_reset_desc_list);
501
502 /*
503 * free the buffer allocated for the VPDMA descriptor list, this should be
504 * called when the user doesn't want to use VPDMA any more.
505 */
vpdma_free_desc_list(struct vpdma_desc_list * list)506 void vpdma_free_desc_list(struct vpdma_desc_list *list)
507 {
508 vpdma_free_desc_buf(&list->buf);
509
510 list->next = NULL;
511 }
512 EXPORT_SYMBOL(vpdma_free_desc_list);
513
vpdma_list_busy(struct vpdma_data * vpdma,int list_num)514 bool vpdma_list_busy(struct vpdma_data *vpdma, int list_num)
515 {
516 return read_reg(vpdma, VPDMA_LIST_STAT_SYNC) & BIT(list_num + 16);
517 }
518 EXPORT_SYMBOL(vpdma_list_busy);
519
520 /*
521 * submit a list of DMA descriptors to the VPE VPDMA, do not wait for completion
522 */
vpdma_submit_descs(struct vpdma_data * vpdma,struct vpdma_desc_list * list,int list_num)523 int vpdma_submit_descs(struct vpdma_data *vpdma,
524 struct vpdma_desc_list *list, int list_num)
525 {
526 int list_size;
527 unsigned long flags;
528
529 if (vpdma_list_busy(vpdma, list_num))
530 return -EBUSY;
531
532 /* 16-byte granularity */
533 list_size = (list->next - list->buf.addr) >> 4;
534
535 spin_lock_irqsave(&vpdma->lock, flags);
536 write_reg(vpdma, VPDMA_LIST_ADDR, (u32) list->buf.dma_addr);
537
538 write_reg(vpdma, VPDMA_LIST_ATTR,
539 (list_num << VPDMA_LIST_NUM_SHFT) |
540 (list->type << VPDMA_LIST_TYPE_SHFT) |
541 list_size);
542 spin_unlock_irqrestore(&vpdma->lock, flags);
543
544 return 0;
545 }
546 EXPORT_SYMBOL(vpdma_submit_descs);
547
548 static void dump_dtd(struct vpdma_dtd *dtd);
549
vpdma_update_dma_addr(struct vpdma_data * vpdma,struct vpdma_desc_list * list,dma_addr_t dma_addr,void * write_dtd,int drop,int idx)550 void vpdma_update_dma_addr(struct vpdma_data *vpdma,
551 struct vpdma_desc_list *list, dma_addr_t dma_addr,
552 void *write_dtd, int drop, int idx)
553 {
554 struct vpdma_dtd *dtd = list->buf.addr;
555 dma_addr_t write_desc_addr;
556 int offset;
557
558 dtd += idx;
559 vpdma_unmap_desc_buf(vpdma, &list->buf);
560
561 dtd->start_addr = dma_addr;
562
563 /* Calculate write address from the offset of write_dtd from start
564 * of the list->buf
565 */
566 offset = (void *)write_dtd - list->buf.addr;
567 write_desc_addr = list->buf.dma_addr + offset;
568
569 if (drop)
570 dtd->desc_write_addr = dtd_desc_write_addr(write_desc_addr,
571 1, 1, 0);
572 else
573 dtd->desc_write_addr = dtd_desc_write_addr(write_desc_addr,
574 1, 0, 0);
575
576 vpdma_map_desc_buf(vpdma, &list->buf);
577
578 dump_dtd(dtd);
579 }
580 EXPORT_SYMBOL(vpdma_update_dma_addr);
581
vpdma_set_max_size(struct vpdma_data * vpdma,int reg_addr,u32 width,u32 height)582 void vpdma_set_max_size(struct vpdma_data *vpdma, int reg_addr,
583 u32 width, u32 height)
584 {
585 if (reg_addr != VPDMA_MAX_SIZE1 && reg_addr != VPDMA_MAX_SIZE2 &&
586 reg_addr != VPDMA_MAX_SIZE3)
587 reg_addr = VPDMA_MAX_SIZE1;
588
589 write_field_reg(vpdma, reg_addr, width - 1,
590 VPDMA_MAX_SIZE_WIDTH_MASK, VPDMA_MAX_SIZE_WIDTH_SHFT);
591
592 write_field_reg(vpdma, reg_addr, height - 1,
593 VPDMA_MAX_SIZE_HEIGHT_MASK, VPDMA_MAX_SIZE_HEIGHT_SHFT);
594
595 }
596 EXPORT_SYMBOL(vpdma_set_max_size);
597
dump_cfd(struct vpdma_cfd * cfd)598 static void dump_cfd(struct vpdma_cfd *cfd)
599 {
600 int class;
601
602 class = cfd_get_class(cfd);
603
604 pr_debug("config descriptor of payload class: %s\n",
605 class == CFD_CLS_BLOCK ? "simple block" :
606 "address data block");
607
608 if (class == CFD_CLS_BLOCK)
609 pr_debug("word0: dst_addr_offset = 0x%08x\n",
610 cfd->dest_addr_offset);
611
612 if (class == CFD_CLS_BLOCK)
613 pr_debug("word1: num_data_wrds = %d\n", cfd->block_len);
614
615 pr_debug("word2: payload_addr = 0x%08x\n", cfd->payload_addr);
616
617 pr_debug("word3: pkt_type = %d, direct = %d, class = %d, dest = %d, payload_len = %d\n",
618 cfd_get_pkt_type(cfd),
619 cfd_get_direct(cfd), class, cfd_get_dest(cfd),
620 cfd_get_payload_len(cfd));
621 }
622
623 /*
624 * append a configuration descriptor to the given descriptor list, where the
625 * payload is in the form of a simple data block specified in the descriptor
626 * header, this is used to upload scaler coefficients to the scaler module
627 */
vpdma_add_cfd_block(struct vpdma_desc_list * list,int client,struct vpdma_buf * blk,u32 dest_offset)628 void vpdma_add_cfd_block(struct vpdma_desc_list *list, int client,
629 struct vpdma_buf *blk, u32 dest_offset)
630 {
631 struct vpdma_cfd *cfd;
632 int len = blk->size;
633
634 WARN_ON(blk->dma_addr & VPDMA_DESC_ALIGN);
635
636 cfd = list->next;
637 WARN_ON((void *)(cfd + 1) > (list->buf.addr + list->buf.size));
638
639 cfd->dest_addr_offset = dest_offset;
640 cfd->block_len = len;
641 cfd->payload_addr = (u32) blk->dma_addr;
642 cfd->ctl_payload_len = cfd_pkt_payload_len(CFD_INDIRECT, CFD_CLS_BLOCK,
643 client, len >> 4);
644
645 list->next = cfd + 1;
646
647 dump_cfd(cfd);
648 }
649 EXPORT_SYMBOL(vpdma_add_cfd_block);
650
651 /*
652 * append a configuration descriptor to the given descriptor list, where the
653 * payload is in the address data block format, this is used to a configure a
654 * discontiguous set of MMRs
655 */
vpdma_add_cfd_adb(struct vpdma_desc_list * list,int client,struct vpdma_buf * adb)656 void vpdma_add_cfd_adb(struct vpdma_desc_list *list, int client,
657 struct vpdma_buf *adb)
658 {
659 struct vpdma_cfd *cfd;
660 unsigned int len = adb->size;
661
662 WARN_ON(len & VPDMA_ADB_SIZE_ALIGN);
663 WARN_ON(adb->dma_addr & VPDMA_DESC_ALIGN);
664
665 cfd = list->next;
666 BUG_ON((void *)(cfd + 1) > (list->buf.addr + list->buf.size));
667
668 cfd->w0 = 0;
669 cfd->w1 = 0;
670 cfd->payload_addr = (u32) adb->dma_addr;
671 cfd->ctl_payload_len = cfd_pkt_payload_len(CFD_INDIRECT, CFD_CLS_ADB,
672 client, len >> 4);
673
674 list->next = cfd + 1;
675
676 dump_cfd(cfd);
677 };
678 EXPORT_SYMBOL(vpdma_add_cfd_adb);
679
680 /*
681 * control descriptor format change based on what type of control descriptor it
682 * is, we only use 'sync on channel' control descriptors for now, so assume it's
683 * that
684 */
dump_ctd(struct vpdma_ctd * ctd)685 static void dump_ctd(struct vpdma_ctd *ctd)
686 {
687 pr_debug("control descriptor\n");
688
689 pr_debug("word3: pkt_type = %d, source = %d, ctl_type = %d\n",
690 ctd_get_pkt_type(ctd), ctd_get_source(ctd), ctd_get_ctl(ctd));
691 }
692
693 /*
694 * append a 'sync on channel' type control descriptor to the given descriptor
695 * list, this descriptor stalls the VPDMA list till the time DMA is completed
696 * on the specified channel
697 */
vpdma_add_sync_on_channel_ctd(struct vpdma_desc_list * list,enum vpdma_channel chan)698 void vpdma_add_sync_on_channel_ctd(struct vpdma_desc_list *list,
699 enum vpdma_channel chan)
700 {
701 struct vpdma_ctd *ctd;
702
703 ctd = list->next;
704 WARN_ON((void *)(ctd + 1) > (list->buf.addr + list->buf.size));
705
706 ctd->w0 = 0;
707 ctd->w1 = 0;
708 ctd->w2 = 0;
709 ctd->type_source_ctl = ctd_type_source_ctl(chan_info[chan].num,
710 CTD_TYPE_SYNC_ON_CHANNEL);
711
712 list->next = ctd + 1;
713
714 dump_ctd(ctd);
715 }
716 EXPORT_SYMBOL(vpdma_add_sync_on_channel_ctd);
717
718 /*
719 * append an 'abort_channel' type control descriptor to the given descriptor
720 * list, this descriptor aborts any DMA transaction happening using the
721 * specified channel
722 */
vpdma_add_abort_channel_ctd(struct vpdma_desc_list * list,int chan_num)723 void vpdma_add_abort_channel_ctd(struct vpdma_desc_list *list,
724 int chan_num)
725 {
726 struct vpdma_ctd *ctd;
727
728 ctd = list->next;
729 WARN_ON((void *)(ctd + 1) > (list->buf.addr + list->buf.size));
730
731 ctd->w0 = 0;
732 ctd->w1 = 0;
733 ctd->w2 = 0;
734 ctd->type_source_ctl = ctd_type_source_ctl(chan_num,
735 CTD_TYPE_ABORT_CHANNEL);
736
737 list->next = ctd + 1;
738
739 dump_ctd(ctd);
740 }
741 EXPORT_SYMBOL(vpdma_add_abort_channel_ctd);
742
dump_dtd(struct vpdma_dtd * dtd)743 static void dump_dtd(struct vpdma_dtd *dtd)
744 {
745 int dir, chan;
746
747 dir = dtd_get_dir(dtd);
748 chan = dtd_get_chan(dtd);
749
750 pr_debug("%s data transfer descriptor for channel %d\n",
751 dir == DTD_DIR_OUT ? "outbound" : "inbound", chan);
752
753 pr_debug("word0: data_type = %d, notify = %d, field = %d, 1D = %d, even_ln_skp = %d, odd_ln_skp = %d, line_stride = %d\n",
754 dtd_get_data_type(dtd), dtd_get_notify(dtd), dtd_get_field(dtd),
755 dtd_get_1d(dtd), dtd_get_even_line_skip(dtd),
756 dtd_get_odd_line_skip(dtd), dtd_get_line_stride(dtd));
757
758 if (dir == DTD_DIR_IN)
759 pr_debug("word1: line_length = %d, xfer_height = %d\n",
760 dtd_get_line_length(dtd), dtd_get_xfer_height(dtd));
761
762 pr_debug("word2: start_addr = %pad\n", &dtd->start_addr);
763
764 pr_debug("word3: pkt_type = %d, mode = %d, dir = %d, chan = %d, pri = %d, next_chan = %d\n",
765 dtd_get_pkt_type(dtd),
766 dtd_get_mode(dtd), dir, chan, dtd_get_priority(dtd),
767 dtd_get_next_chan(dtd));
768
769 if (dir == DTD_DIR_IN)
770 pr_debug("word4: frame_width = %d, frame_height = %d\n",
771 dtd_get_frame_width(dtd), dtd_get_frame_height(dtd));
772 else
773 pr_debug("word4: desc_write_addr = 0x%08x, write_desc = %d, drp_data = %d, use_desc_reg = %d\n",
774 dtd_get_desc_write_addr(dtd), dtd_get_write_desc(dtd),
775 dtd_get_drop_data(dtd), dtd_get_use_desc(dtd));
776
777 if (dir == DTD_DIR_IN)
778 pr_debug("word5: hor_start = %d, ver_start = %d\n",
779 dtd_get_h_start(dtd), dtd_get_v_start(dtd));
780 else
781 pr_debug("word5: max_width %d, max_height %d\n",
782 dtd_get_max_width(dtd), dtd_get_max_height(dtd));
783
784 pr_debug("word6: client specific attr0 = 0x%08x\n", dtd->client_attr0);
785 pr_debug("word7: client specific attr1 = 0x%08x\n", dtd->client_attr1);
786 }
787
788 /*
789 * append an outbound data transfer descriptor to the given descriptor list,
790 * this sets up a 'client to memory' VPDMA transfer for the given VPDMA channel
791 *
792 * @list: vpdma desc list to which we add this descriptor
793 * @width: width of the image in pixels in memory
794 * @c_rect: compose params of output image
795 * @fmt: vpdma data format of the buffer
796 * dma_addr: dma address as seen by VPDMA
797 * max_width: enum for maximum width of data transfer
798 * max_height: enum for maximum height of data transfer
799 * chan: VPDMA channel
800 * flags: VPDMA flags to configure some descriptor fields
801 */
vpdma_add_out_dtd(struct vpdma_desc_list * list,int width,int stride,const struct v4l2_rect * c_rect,const struct vpdma_data_format * fmt,dma_addr_t dma_addr,int max_w,int max_h,enum vpdma_channel chan,u32 flags)802 void vpdma_add_out_dtd(struct vpdma_desc_list *list, int width,
803 int stride, const struct v4l2_rect *c_rect,
804 const struct vpdma_data_format *fmt, dma_addr_t dma_addr,
805 int max_w, int max_h, enum vpdma_channel chan, u32 flags)
806 {
807 vpdma_rawchan_add_out_dtd(list, width, stride, c_rect, fmt, dma_addr,
808 max_w, max_h, chan_info[chan].num, flags);
809 }
810 EXPORT_SYMBOL(vpdma_add_out_dtd);
811
vpdma_rawchan_add_out_dtd(struct vpdma_desc_list * list,int width,int stride,const struct v4l2_rect * c_rect,const struct vpdma_data_format * fmt,dma_addr_t dma_addr,int max_w,int max_h,int raw_vpdma_chan,u32 flags)812 void vpdma_rawchan_add_out_dtd(struct vpdma_desc_list *list, int width,
813 int stride, const struct v4l2_rect *c_rect,
814 const struct vpdma_data_format *fmt, dma_addr_t dma_addr,
815 int max_w, int max_h, int raw_vpdma_chan, u32 flags)
816 {
817 int priority = 0;
818 int field = 0;
819 int notify = 1;
820 int channel, next_chan;
821 struct v4l2_rect rect = *c_rect;
822 int depth = fmt->depth;
823 struct vpdma_dtd *dtd;
824
825 channel = next_chan = raw_vpdma_chan;
826
827 if (fmt->type == VPDMA_DATA_FMT_TYPE_YUV &&
828 fmt->data_type == DATA_TYPE_C420) {
829 rect.height >>= 1;
830 rect.top >>= 1;
831 depth = 8;
832 }
833
834 dma_addr += rect.top * stride + (rect.left * depth >> 3);
835
836 dtd = list->next;
837 WARN_ON((void *)(dtd + 1) > (list->buf.addr + list->buf.size));
838
839 dtd->type_ctl_stride = dtd_type_ctl_stride(fmt->data_type,
840 notify,
841 field,
842 !!(flags & VPDMA_DATA_FRAME_1D),
843 !!(flags & VPDMA_DATA_EVEN_LINE_SKIP),
844 !!(flags & VPDMA_DATA_ODD_LINE_SKIP),
845 stride);
846 dtd->w1 = 0;
847 dtd->start_addr = (u32) dma_addr;
848 dtd->pkt_ctl = dtd_pkt_ctl(!!(flags & VPDMA_DATA_MODE_TILED),
849 DTD_DIR_OUT, channel, priority, next_chan);
850 dtd->desc_write_addr = dtd_desc_write_addr(0, 0, 0, 0);
851 dtd->max_width_height = dtd_max_width_height(max_w, max_h);
852 dtd->client_attr0 = 0;
853 dtd->client_attr1 = 0;
854
855 list->next = dtd + 1;
856
857 dump_dtd(dtd);
858 }
859 EXPORT_SYMBOL(vpdma_rawchan_add_out_dtd);
860
861 /*
862 * append an inbound data transfer descriptor to the given descriptor list,
863 * this sets up a 'memory to client' VPDMA transfer for the given VPDMA channel
864 *
865 * @list: vpdma desc list to which we add this descriptor
866 * @width: width of the image in pixels in memory(not the cropped width)
867 * @c_rect: crop params of input image
868 * @fmt: vpdma data format of the buffer
869 * dma_addr: dma address as seen by VPDMA
870 * chan: VPDMA channel
871 * field: top or bottom field info of the input image
872 * flags: VPDMA flags to configure some descriptor fields
873 * frame_width/height: the complete width/height of the image presented to the
874 * client (this makes sense when multiple channels are
875 * connected to the same client, forming a larger frame)
876 * start_h, start_v: position where the given channel starts providing pixel
877 * data to the client (makes sense when multiple channels
878 * contribute to the client)
879 */
vpdma_add_in_dtd(struct vpdma_desc_list * list,int width,int stride,const struct v4l2_rect * c_rect,const struct vpdma_data_format * fmt,dma_addr_t dma_addr,enum vpdma_channel chan,int field,u32 flags,int frame_width,int frame_height,int start_h,int start_v)880 void vpdma_add_in_dtd(struct vpdma_desc_list *list, int width,
881 int stride, const struct v4l2_rect *c_rect,
882 const struct vpdma_data_format *fmt, dma_addr_t dma_addr,
883 enum vpdma_channel chan, int field, u32 flags, int frame_width,
884 int frame_height, int start_h, int start_v)
885 {
886 int priority = 0;
887 int notify = 1;
888 int depth = fmt->depth;
889 int channel, next_chan;
890 struct v4l2_rect rect = *c_rect;
891 struct vpdma_dtd *dtd;
892
893 channel = next_chan = chan_info[chan].num;
894
895 if (fmt->type == VPDMA_DATA_FMT_TYPE_YUV &&
896 fmt->data_type == DATA_TYPE_C420) {
897 rect.height >>= 1;
898 rect.top >>= 1;
899 depth = 8;
900 }
901
902 dma_addr += rect.top * stride + (rect.left * depth >> 3);
903
904 dtd = list->next;
905 WARN_ON((void *)(dtd + 1) > (list->buf.addr + list->buf.size));
906
907 dtd->type_ctl_stride = dtd_type_ctl_stride(fmt->data_type,
908 notify,
909 field,
910 !!(flags & VPDMA_DATA_FRAME_1D),
911 !!(flags & VPDMA_DATA_EVEN_LINE_SKIP),
912 !!(flags & VPDMA_DATA_ODD_LINE_SKIP),
913 stride);
914
915 dtd->xfer_length_height = dtd_xfer_length_height(rect.width,
916 rect.height);
917 dtd->start_addr = (u32) dma_addr;
918 dtd->pkt_ctl = dtd_pkt_ctl(!!(flags & VPDMA_DATA_MODE_TILED),
919 DTD_DIR_IN, channel, priority, next_chan);
920 dtd->frame_width_height = dtd_frame_width_height(frame_width,
921 frame_height);
922 dtd->start_h_v = dtd_start_h_v(start_h, start_v);
923 dtd->client_attr0 = 0;
924 dtd->client_attr1 = 0;
925
926 list->next = dtd + 1;
927
928 dump_dtd(dtd);
929 }
930 EXPORT_SYMBOL(vpdma_add_in_dtd);
931
vpdma_hwlist_alloc(struct vpdma_data * vpdma,void * priv)932 int vpdma_hwlist_alloc(struct vpdma_data *vpdma, void *priv)
933 {
934 int i, list_num = -1;
935 unsigned long flags;
936
937 spin_lock_irqsave(&vpdma->lock, flags);
938 for (i = 0; i < VPDMA_MAX_NUM_LIST &&
939 vpdma->hwlist_used[i] == true; i++)
940 ;
941
942 if (i < VPDMA_MAX_NUM_LIST) {
943 list_num = i;
944 vpdma->hwlist_used[i] = true;
945 vpdma->hwlist_priv[i] = priv;
946 }
947 spin_unlock_irqrestore(&vpdma->lock, flags);
948
949 return list_num;
950 }
951 EXPORT_SYMBOL(vpdma_hwlist_alloc);
952
vpdma_hwlist_get_priv(struct vpdma_data * vpdma,int list_num)953 void *vpdma_hwlist_get_priv(struct vpdma_data *vpdma, int list_num)
954 {
955 if (!vpdma || list_num >= VPDMA_MAX_NUM_LIST)
956 return NULL;
957
958 return vpdma->hwlist_priv[list_num];
959 }
960 EXPORT_SYMBOL(vpdma_hwlist_get_priv);
961
vpdma_hwlist_release(struct vpdma_data * vpdma,int list_num)962 void *vpdma_hwlist_release(struct vpdma_data *vpdma, int list_num)
963 {
964 void *priv;
965 unsigned long flags;
966
967 spin_lock_irqsave(&vpdma->lock, flags);
968 vpdma->hwlist_used[list_num] = false;
969 priv = vpdma->hwlist_priv;
970 spin_unlock_irqrestore(&vpdma->lock, flags);
971
972 return priv;
973 }
974 EXPORT_SYMBOL(vpdma_hwlist_release);
975
976 /* set or clear the mask for list complete interrupt */
vpdma_enable_list_complete_irq(struct vpdma_data * vpdma,int irq_num,int list_num,bool enable)977 void vpdma_enable_list_complete_irq(struct vpdma_data *vpdma, int irq_num,
978 int list_num, bool enable)
979 {
980 u32 reg_addr = VPDMA_INT_LIST0_MASK + VPDMA_INTX_OFFSET * irq_num;
981 u32 val;
982
983 val = read_reg(vpdma, reg_addr);
984 if (enable)
985 val |= (1 << (list_num * 2));
986 else
987 val &= ~(1 << (list_num * 2));
988 write_reg(vpdma, reg_addr, val);
989 }
990 EXPORT_SYMBOL(vpdma_enable_list_complete_irq);
991
992 /* get the LIST_STAT register */
vpdma_get_list_stat(struct vpdma_data * vpdma,int irq_num)993 unsigned int vpdma_get_list_stat(struct vpdma_data *vpdma, int irq_num)
994 {
995 u32 reg_addr = VPDMA_INT_LIST0_STAT + VPDMA_INTX_OFFSET * irq_num;
996
997 return read_reg(vpdma, reg_addr);
998 }
999 EXPORT_SYMBOL(vpdma_get_list_stat);
1000
1001 /* get the LIST_MASK register */
vpdma_get_list_mask(struct vpdma_data * vpdma,int irq_num)1002 unsigned int vpdma_get_list_mask(struct vpdma_data *vpdma, int irq_num)
1003 {
1004 u32 reg_addr = VPDMA_INT_LIST0_MASK + VPDMA_INTX_OFFSET * irq_num;
1005
1006 return read_reg(vpdma, reg_addr);
1007 }
1008 EXPORT_SYMBOL(vpdma_get_list_mask);
1009
1010 /* clear previously occurred list interrupts in the LIST_STAT register */
vpdma_clear_list_stat(struct vpdma_data * vpdma,int irq_num,int list_num)1011 void vpdma_clear_list_stat(struct vpdma_data *vpdma, int irq_num,
1012 int list_num)
1013 {
1014 u32 reg_addr = VPDMA_INT_LIST0_STAT + VPDMA_INTX_OFFSET * irq_num;
1015
1016 write_reg(vpdma, reg_addr, 3 << (list_num * 2));
1017 }
1018 EXPORT_SYMBOL(vpdma_clear_list_stat);
1019
vpdma_set_bg_color(struct vpdma_data * vpdma,struct vpdma_data_format * fmt,u32 color)1020 void vpdma_set_bg_color(struct vpdma_data *vpdma,
1021 struct vpdma_data_format *fmt, u32 color)
1022 {
1023 if (fmt->type == VPDMA_DATA_FMT_TYPE_RGB)
1024 write_reg(vpdma, VPDMA_BG_RGB, color);
1025 else if (fmt->type == VPDMA_DATA_FMT_TYPE_YUV)
1026 write_reg(vpdma, VPDMA_BG_YUV, color);
1027 }
1028 EXPORT_SYMBOL(vpdma_set_bg_color);
1029
1030 /*
1031 * configures the output mode of the line buffer for the given client, the
1032 * line buffer content can either be mirrored(each line repeated twice) or
1033 * passed to the client as is
1034 */
vpdma_set_line_mode(struct vpdma_data * vpdma,int line_mode,enum vpdma_channel chan)1035 void vpdma_set_line_mode(struct vpdma_data *vpdma, int line_mode,
1036 enum vpdma_channel chan)
1037 {
1038 int client_cstat = chan_info[chan].cstat_offset;
1039
1040 write_field_reg(vpdma, client_cstat, line_mode,
1041 VPDMA_CSTAT_LINE_MODE_MASK, VPDMA_CSTAT_LINE_MODE_SHIFT);
1042 }
1043 EXPORT_SYMBOL(vpdma_set_line_mode);
1044
1045 /*
1046 * configures the event which should trigger VPDMA transfer for the given
1047 * client
1048 */
vpdma_set_frame_start_event(struct vpdma_data * vpdma,enum vpdma_frame_start_event fs_event,enum vpdma_channel chan)1049 void vpdma_set_frame_start_event(struct vpdma_data *vpdma,
1050 enum vpdma_frame_start_event fs_event,
1051 enum vpdma_channel chan)
1052 {
1053 int client_cstat = chan_info[chan].cstat_offset;
1054
1055 write_field_reg(vpdma, client_cstat, fs_event,
1056 VPDMA_CSTAT_FRAME_START_MASK, VPDMA_CSTAT_FRAME_START_SHIFT);
1057 }
1058 EXPORT_SYMBOL(vpdma_set_frame_start_event);
1059
vpdma_firmware_cb(const struct firmware * f,void * context)1060 static void vpdma_firmware_cb(const struct firmware *f, void *context)
1061 {
1062 struct vpdma_data *vpdma = context;
1063 struct vpdma_buf fw_dma_buf;
1064 int i, r;
1065
1066 dev_dbg(&vpdma->pdev->dev, "firmware callback\n");
1067
1068 if (!f || !f->data) {
1069 dev_err(&vpdma->pdev->dev, "couldn't get firmware\n");
1070 return;
1071 }
1072
1073 /* already initialized */
1074 if (read_field_reg(vpdma, VPDMA_LIST_ATTR, VPDMA_LIST_RDY_MASK,
1075 VPDMA_LIST_RDY_SHFT)) {
1076 vpdma->cb(vpdma->pdev);
1077 return;
1078 }
1079
1080 r = vpdma_alloc_desc_buf(&fw_dma_buf, f->size);
1081 if (r) {
1082 dev_err(&vpdma->pdev->dev,
1083 "failed to allocate dma buffer for firmware\n");
1084 goto rel_fw;
1085 }
1086
1087 memcpy(fw_dma_buf.addr, f->data, f->size);
1088
1089 vpdma_map_desc_buf(vpdma, &fw_dma_buf);
1090
1091 write_reg(vpdma, VPDMA_LIST_ADDR, (u32) fw_dma_buf.dma_addr);
1092
1093 for (i = 0; i < 100; i++) { /* max 1 second */
1094 msleep_interruptible(10);
1095
1096 if (read_field_reg(vpdma, VPDMA_LIST_ATTR, VPDMA_LIST_RDY_MASK,
1097 VPDMA_LIST_RDY_SHFT))
1098 break;
1099 }
1100
1101 if (i == 100) {
1102 dev_err(&vpdma->pdev->dev, "firmware upload failed\n");
1103 goto free_buf;
1104 }
1105
1106 vpdma->cb(vpdma->pdev);
1107
1108 free_buf:
1109 vpdma_unmap_desc_buf(vpdma, &fw_dma_buf);
1110
1111 vpdma_free_desc_buf(&fw_dma_buf);
1112 rel_fw:
1113 release_firmware(f);
1114 }
1115
vpdma_load_firmware(struct vpdma_data * vpdma)1116 static int vpdma_load_firmware(struct vpdma_data *vpdma)
1117 {
1118 int r;
1119 struct device *dev = &vpdma->pdev->dev;
1120
1121 r = request_firmware_nowait(THIS_MODULE, 1,
1122 (const char *) VPDMA_FIRMWARE, dev, GFP_KERNEL, vpdma,
1123 vpdma_firmware_cb);
1124 if (r) {
1125 dev_err(dev, "firmware not available %s\n", VPDMA_FIRMWARE);
1126 return r;
1127 } else {
1128 dev_info(dev, "loading firmware %s\n", VPDMA_FIRMWARE);
1129 }
1130
1131 return 0;
1132 }
1133
vpdma_create(struct platform_device * pdev,struct vpdma_data * vpdma,void (* cb)(struct platform_device * pdev))1134 int vpdma_create(struct platform_device *pdev, struct vpdma_data *vpdma,
1135 void (*cb)(struct platform_device *pdev))
1136 {
1137 struct resource *res;
1138 int r;
1139
1140 dev_dbg(&pdev->dev, "vpdma_create\n");
1141
1142 vpdma->pdev = pdev;
1143 vpdma->cb = cb;
1144 spin_lock_init(&vpdma->lock);
1145
1146 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpdma");
1147 if (res == NULL) {
1148 dev_err(&pdev->dev, "missing platform resources data\n");
1149 return -ENODEV;
1150 }
1151
1152 vpdma->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1153 if (!vpdma->base) {
1154 dev_err(&pdev->dev, "failed to ioremap\n");
1155 return -ENOMEM;
1156 }
1157
1158 r = vpdma_load_firmware(vpdma);
1159 if (r) {
1160 pr_err("failed to load firmware %s\n", VPDMA_FIRMWARE);
1161 return r;
1162 }
1163
1164 return 0;
1165 }
1166 EXPORT_SYMBOL(vpdma_create);
1167
1168 MODULE_AUTHOR("Texas Instruments Inc.");
1169 MODULE_FIRMWARE(VPDMA_FIRMWARE);
1170 MODULE_LICENSE("GPL v2");
1171