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Searched refs:IS_FPGA_MAXIMUS_DC (Results 1 – 23 of 23) sorted by relevance

/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_hwss.c372 if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) in dp_set_dsc_on_rx()
421 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in dp_set_dsc_on_stream()
446 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in dp_set_dsc_on_stream()
508 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in dp_set_dsc_pps_sdp()
517 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in dp_set_dsc_pps_sdp()
Ddc_link_dp.c3453 IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment)) in dp_set_fec_ready()
3489 IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment)) in dp_set_fec_enable()
Ddc_link.c2720 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in core_link_enable_stream()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
Ddce112_clk_mgr.c113 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in dce112_set_clock()
155 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in dce112_set_dispclk()
/drivers/gpu/drm/amd/display/dc/gpio/
Dhw_translate.c67 if (IS_FPGA_MAXIMUS_DC(dce_environment)) { in dal_hw_translate_init()
Dhw_factory.c69 if (IS_FPGA_MAXIMUS_DC(dce_environment)) { in dal_hw_factory_init()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr_vbios_smu.c103 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in rv1_vbios_smu_set_dispclk()
/drivers/gpu/drm/amd/display/dc/dce112/
Ddce112_hw_sequencer.c123 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in dce112_enable_display_power_gating()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr_vbios_smu.c98 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in rn_vbios_smu_set_dispclk()
Drn_clk_mgr.c535 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { in rn_clk_mgr_construct()
/drivers/gpu/drm/amd/display/dc/
Ddc_types.h58 #define IS_FPGA_MAXIMUS_DC(dce_environment) \ macro
62 (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
Ddc_helper.c319 !IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in generic_reg_wait()
331 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in generic_reg_wait()
/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_hw_sequencer.c162 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in dce120_enable_display_power_gating()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c828 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_reset_back_end_for_pipe()
1191 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_init_hw()
1220 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_init_hw()
2694 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_prepare_bandwidth()
2726 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_optimize_bandwidth()
Ddcn10_resource.c1540 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? in construct()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c449 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { in dcn20_clk_mgr_construct()
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c1448 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) in construct()
1644 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? in construct()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clk_mgr.c329 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in dce112_set_clock()
Ddce_clock_source.c909 if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) { in dce112_program_pix_clk()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dsc.c699 if (IS_FPGA_MAXIMUS_DC(dsc20->base.ctx->dce_environment)) { in dsc_write_to_registers()
Ddcn20_hwseq.c1637 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn20_reset_back_end_for_pipe()
2154 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn20_hw_sequencer_construct()
Ddcn20_resource.c3606 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? in construct()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c203 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in dce110_enable_display_power_gating()