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Searched refs:TIME_STAMP_INT_ENABLE (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/radeon/
Dcik.c7066 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7067 cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7068 cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7069 cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7070 cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7071 cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7072 cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7073 cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7078 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7086 cp_m1p0 |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
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Dcikd.h1337 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
1369 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
Dnid.h497 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
Devergreen.c4525 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4529 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4533 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4539 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
Dsid.h1282 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
Devergreend.h1250 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
Dsi.c6083 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6087 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6091 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; in si_irq_set()
Dr600d.h718 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
Dr600.c3825 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in r600_irq_set()
/drivers/gpu/drm/amd/amdgpu/
Dgfx_v10_0.c4882 TIME_STAMP_INT_ENABLE, 0); in gfx_v10_0_set_gfx_eop_interrupt_state()
4888 TIME_STAMP_INT_ENABLE, 1); in gfx_v10_0_set_gfx_eop_interrupt_state()
4935 TIME_STAMP_INT_ENABLE, 0); in gfx_v10_0_set_compute_eop_interrupt_state()
4941 TIME_STAMP_INT_ENABLE, 1); in gfx_v10_0_set_compute_eop_interrupt_state()
Dsid.h1311 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
Dgfx_v9_0.c5487 TIME_STAMP_INT_ENABLE, in gfx_v9_0_set_gfx_eop_interrupt_state()
5534 TIME_STAMP_INT_ENABLE, 0); in gfx_v9_0_set_compute_eop_interrupt_state()
5540 TIME_STAMP_INT_ENABLE, 1); in gfx_v9_0_set_compute_eop_interrupt_state()
Dgfx_v8_0.c6540 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE, in gfx_v8_0_set_gfx_eop_interrupt_state()