| /drivers/net/wireless/quantenna/qtnfmac/pcie/ |
| D | pearl_pcie_regs.h | 8 #define PCIE_HDP_CTRL(base) ((base) + 0x2c00) argument
9 #define PCIE_HDP_AXI_CTRL(base) ((base) + 0x2c04) argument
10 #define PCIE_HDP_HOST_WR_DESC0(base) ((base) + 0x2c10) argument
11 #define PCIE_HDP_HOST_WR_DESC0_H(base) ((base) + 0x2c14) argument
12 #define PCIE_HDP_HOST_WR_DESC1(base) ((base) + 0x2c18) argument
13 #define PCIE_HDP_HOST_WR_DESC1_H(base) ((base) + 0x2c1c) argument
14 #define PCIE_HDP_HOST_WR_DESC2(base) ((base) + 0x2c20) argument
15 #define PCIE_HDP_HOST_WR_DESC2_H(base) ((base) + 0x2c24) argument
16 #define PCIE_HDP_HOST_WR_DESC3(base) ((base) + 0x2c28) argument
17 #define PCIE_HDP_HOST_WR_DESC4_H(base) ((base) + 0x2c2c) argument
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| D | topaz_pcie_regs.h | 8 #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc) argument
9 #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4) argument
10 #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8) argument
11 #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc) argument
12 #define PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(base) ((base) + 0x9D0) argument
13 #define PCIE_DMA_WR_DONE_IMWR_ADDR_HIGH(base) ((base) + 0x9d4) argument
15 #define PCIE_DMA_RD_INTR_STATUS(base) ((base) + 0x310) argument
16 #define PCIE_DMA_RD_INTR_MASK(base) ((base) + 0x319) argument
17 #define PCIE_DMA_RD_INTR_CLR(base) ((base) + 0x31c) argument
18 #define PCIE_DMA_RD_ERR_STATUS_LOW(base) ((base) + 0x324) argument
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| /drivers/clk/imx/ |
| D | clk-imx7d.c | 394 void __iomem *base; in imx7d_clocks_init() local
410 base = of_iomap(np, 0); in imx7d_clocks_init()
411 WARN_ON(!base); in imx7d_clocks_init()
414 …hws[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_s… in imx7d_clocks_init()
415 …hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_… in imx7d_clocks_init()
416 …hws[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_hw_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_s… in imx7d_clocks_init()
417 …hws[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_hw_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_… in imx7d_clocks_init()
418 …hws[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_hw_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypas… in imx7d_clocks_init()
419 …hws[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_hw_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypa… in imx7d_clocks_init()
421 …hws[IMX7D_PLL_ARM_MAIN] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "osc", base + 0x60, 0x7… in imx7d_clocks_init()
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| D | clk-imx6ul.c | 117 void __iomem *base; in imx6ul_clocks_init() local
137 base = of_iomap(np, 0); in imx6ul_clocks_init()
139 WARN_ON(!base); in imx6ul_clocks_init()
141 …hws[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
142 …hws[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
143 …hws[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
144 …hws[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
145 …hws[IMX6UL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
146 …hws[IMX6UL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
147 …hws[IMX6UL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
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| D | clk-imx8mq.c | 287 void __iomem *base; in imx8mq_clocks_probe() local
300 base = of_iomap(np, 0); in imx8mq_clocks_probe()
301 if (WARN_ON(!base)) in imx8mq_clocks_probe()
304 …clks[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, AR… in imx8mq_clocks_probe()
305 …clks[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, AR… in imx8mq_clocks_probe()
306 …clks[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, AR… in imx8mq_clocks_probe()
307 …clks[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_sel… in imx8mq_clocks_probe()
308 …clks[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_sel… in imx8mq_clocks_probe()
309 …clks[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_se… in imx8mq_clocks_probe()
310 …clks[IMX8MQ_SYS1_PLL1_REF_SEL] = imx_clk_mux("sys1_pll1_ref_sel", base + 0x30, 0, 2, pll_ref_sels,… in imx8mq_clocks_probe()
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| D | clk-imx6sll.c | 97 void __iomem *base; in imx6sll_clocks_init() local
118 base = of_iomap(np, 0); in imx6sll_clocks_init()
120 WARN_ON(!base); in imx6sll_clocks_init()
123 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x0)); in imx6sll_clocks_init()
124 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x10)); in imx6sll_clocks_init()
125 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x20)); in imx6sll_clocks_init()
126 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x30)); in imx6sll_clocks_init()
127 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x70)); in imx6sll_clocks_init()
128 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xa0)); in imx6sll_clocks_init()
129 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xe0)); in imx6sll_clocks_init()
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| D | clk-imx6sx.c | 129 void __iomem *base; in imx6sx_clocks_init() local
154 base = of_iomap(np, 0); in imx6sx_clocks_init()
155 WARN_ON(!base); in imx6sx_clocks_init()
158 …hws[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
159 …hws[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
160 …hws[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
161 …hws[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
162 …hws[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
163 …hws[IMX6SX_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
164 …hws[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
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| D | clk-imx8mm.c | 372 void __iomem *base; in imx8mm_clocks_probe() local
384 base = of_iomap(np, 0); in imx8mm_clocks_probe()
385 if (WARN_ON(!base)) in imx8mm_clocks_probe()
388 …clks[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels… in imx8mm_clocks_probe()
389 …clks[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sel… in imx8mm_clocks_probe()
390 …clks[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sel… in imx8mm_clocks_probe()
391 …clks[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
392 …clks[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARR… in imx8mm_clocks_probe()
393 …clks[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARR… in imx8mm_clocks_probe()
394 …clks[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARR… in imx8mm_clocks_probe()
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| D | clk-imx6sl.c | 190 void __iomem *base; in imx6sl_clocks_init() local
209 base = of_iomap(np, 0); in imx6sl_clocks_init()
210 WARN_ON(!base); in imx6sl_clocks_init()
211 anatop_base = base; in imx6sl_clocks_init()
213 …hws[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
214 …hws[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
215 …hws[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
216 …hws[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
217 …hws[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
218 …hws[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
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| D | clk-imx8mn.c | 383 void __iomem *base; in imx8mn_clocks_probe() local
395 base = of_iomap(np, 0); in imx8mn_clocks_probe()
396 if (WARN_ON(!base)) { in imx8mn_clocks_probe()
401 …clks[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels… in imx8mn_clocks_probe()
402 …clks[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sel… in imx8mn_clocks_probe()
403 …clks[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sel… in imx8mn_clocks_probe()
404 …clks[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
405 …clks[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARR… in imx8mn_clocks_probe()
406 …clks[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARR… in imx8mn_clocks_probe()
407 …clks[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARR… in imx8mn_clocks_probe()
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| D | clk-imx6q.c | 440 void __iomem *anatop_base, *base; in imx6q_clocks_init() local
463 anatop_base = base = of_iomap(np, 0); in imx6q_clocks_init()
464 WARN_ON(!base); in imx6q_clocks_init()
475 …hws[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_sr… in imx6q_clocks_init()
476 …hws[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_sr… in imx6q_clocks_init()
477 …hws[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_sr… in imx6q_clocks_init()
478 …hws[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_sr… in imx6q_clocks_init()
479 …hws[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_sr… in imx6q_clocks_init()
480 …hws[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_sr… in imx6q_clocks_init()
481 …hws[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_sr… in imx6q_clocks_init()
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| D | clk-imx7ulp.c | 63 void __iomem *base; in imx7ulp_clk_scg1_init() local
83 base = of_iomap(np, 0); in imx7ulp_clk_scg1_init()
84 WARN_ON(!base); in imx7ulp_clk_scg1_init()
87 …clks[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_hw_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_… in imx7ulp_clk_scg1_init()
88 …clks[IMX7ULP_CLK_SPLL_PRE_SEL] = imx_clk_hw_mux_flags("spll_pre_sel", base + 0x608, 0, 1, pll_pre_… in imx7ulp_clk_scg1_init()
91 …clks[IMX7ULP_CLK_APLL_PRE_DIV] = imx_clk_hw_divider_flags("apll_pre_div", "apll_pre_sel", base + 0… in imx7ulp_clk_scg1_init()
92 …clks[IMX7ULP_CLK_SPLL_PRE_DIV] = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0… in imx7ulp_clk_scg1_init()
95 clks[IMX7ULP_CLK_APLL] = imx_clk_pllv4("apll", "apll_pre_div", base + 0x500); in imx7ulp_clk_scg1_init()
96 clks[IMX7ULP_CLK_SPLL] = imx_clk_pllv4("spll", "spll_pre_div", base + 0x600); in imx7ulp_clk_scg1_init()
99 clks[IMX7ULP_CLK_APLL_PFD0] = imx_clk_pfdv2("apll_pfd0", "apll", base + 0x50c, 0); in imx7ulp_clk_scg1_init()
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| /drivers/gpu/drm/omapdrm/dss/ |
| D | hdmi5_core.c | 40 void __iomem *base = core->base; in hdmi_core_ddc_init() local
55 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); in hdmi_core_ddc_init()
56 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ, in hdmi_core_ddc_init()
61 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); in hdmi_core_ddc_init()
65 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init()
67 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init()
72 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, in hdmi_core_ddc_init()
74 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, in hdmi_core_ddc_init()
79 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init()
81 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init()
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| /drivers/video/fbdev/omap2/omapfb/dss/ |
| D | hdmi5_core.c | 41 void __iomem *base = core->base; in hdmi_core_ddc_init() local
56 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); in hdmi_core_ddc_init()
57 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ, in hdmi_core_ddc_init()
62 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); in hdmi_core_ddc_init()
66 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init()
68 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init()
73 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, in hdmi_core_ddc_init()
75 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, in hdmi_core_ddc_init()
80 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init()
82 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init()
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| /drivers/gpu/drm/msm/dsi/phy/ |
| D | dsi_phy_28nm_8960.c | 14 void __iomem *base = phy->base; in dsi_28nm_dphy_set_timing() local
16 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_0, in dsi_28nm_dphy_set_timing()
18 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_1, in dsi_28nm_dphy_set_timing()
20 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_2, in dsi_28nm_dphy_set_timing()
22 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_3, 0x0); in dsi_28nm_dphy_set_timing()
23 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_4, in dsi_28nm_dphy_set_timing()
25 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_5, in dsi_28nm_dphy_set_timing()
27 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_6, in dsi_28nm_dphy_set_timing()
29 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_7, in dsi_28nm_dphy_set_timing()
31 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_8, in dsi_28nm_dphy_set_timing()
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| D | dsi_phy_28nm.c | 12 void __iomem *base = phy->base; in dsi_28nm_dphy_set_timing() local
14 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_0, in dsi_28nm_dphy_set_timing()
16 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_1, in dsi_28nm_dphy_set_timing()
18 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_2, in dsi_28nm_dphy_set_timing()
21 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_3, in dsi_28nm_dphy_set_timing()
23 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_4, in dsi_28nm_dphy_set_timing()
25 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_5, in dsi_28nm_dphy_set_timing()
27 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_6, in dsi_28nm_dphy_set_timing()
29 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_7, in dsi_28nm_dphy_set_timing()
31 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_8, in dsi_28nm_dphy_set_timing()
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| D | dsi_phy_20nm.c | 12 void __iomem *base = phy->base; in dsi_20nm_dphy_set_timing() local
14 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0, in dsi_20nm_dphy_set_timing()
16 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1, in dsi_20nm_dphy_set_timing()
18 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2, in dsi_20nm_dphy_set_timing()
21 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3, in dsi_20nm_dphy_set_timing()
23 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4, in dsi_20nm_dphy_set_timing()
25 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5, in dsi_20nm_dphy_set_timing()
27 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6, in dsi_20nm_dphy_set_timing()
29 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7, in dsi_20nm_dphy_set_timing()
31 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_8, in dsi_20nm_dphy_set_timing()
[all …]
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| /drivers/scsi/ |
| D | nsp32_io.h | 12 static inline void nsp32_write1(unsigned int base, in nsp32_write1() argument
16 outb(val, (base + index)); in nsp32_write1()
19 static inline unsigned char nsp32_read1(unsigned int base, in nsp32_read1() argument
22 return inb(base + index); in nsp32_read1()
25 static inline void nsp32_write2(unsigned int base, in nsp32_write2() argument
29 outw(val, (base + index)); in nsp32_write2()
32 static inline unsigned short nsp32_read2(unsigned int base, in nsp32_read2() argument
35 return inw(base + index); in nsp32_read2()
38 static inline void nsp32_write4(unsigned int base, in nsp32_write4() argument
42 outl(val, (base + index)); in nsp32_write4()
[all …]
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| D | aha1740.h | 19 #define HID0(base) (base + 0x0) argument
20 #define HID1(base) (base + 0x1) argument
21 #define HID2(base) (base + 0x2) argument
22 #define HID3(base) (base + 0x3) argument
23 #define EBCNTRL(base) (base + 0x4) argument
24 #define PORTADR(base) (base + 0x40) argument
25 #define BIOSADR(base) (base + 0x41) argument
26 #define INTDEF(base) (base + 0x42) argument
27 #define SCSIDEF(base) (base + 0x43) argument
28 #define BUSDEF(base) (base + 0x44) argument
[all …]
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| /drivers/gpu/drm/sun4i/ |
| D | sun8i_vi_scaler.h | 30 #define SUN8I_SCALER_VSU_CTRL(base) ((base) + 0x0) argument
31 #define SUN50I_SCALER_VSU_SCALE_MODE(base) ((base) + 0x10) argument
32 #define SUN50I_SCALER_VSU_DIR_THR(base) ((base) + 0x20) argument
33 #define SUN50I_SCALER_VSU_EDGE_THR(base) ((base) + 0x24) argument
34 #define SUN50I_SCALER_VSU_EDSCL_CTRL(base) ((base) + 0x28) argument
35 #define SUN50I_SCALER_VSU_ANGLE_THR(base) ((base) + 0x2c) argument
36 #define SUN8I_SCALER_VSU_OUTSIZE(base) ((base) + 0x40) argument
37 #define SUN8I_SCALER_VSU_YINSIZE(base) ((base) + 0x80) argument
38 #define SUN8I_SCALER_VSU_YHSTEP(base) ((base) + 0x88) argument
39 #define SUN8I_SCALER_VSU_YVSTEP(base) ((base) + 0x8c) argument
[all …]
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| /drivers/staging/isdn/avm/ |
| D | avmcard.h | 219 static inline unsigned char b1outp(unsigned int base, in b1outp() argument
223 outb(value, base + offset); in b1outp()
224 return inb(base + B1_ANALYSE); in b1outp()
228 static inline int b1_rx_full(unsigned int base) in b1_rx_full() argument
230 return inb(base + B1_INSTAT) & 0x1; in b1_rx_full()
233 static inline unsigned char b1_get_byte(unsigned int base) in b1_get_byte() argument
236 while (!b1_rx_full(base) && time_before(jiffies, stop)); in b1_get_byte()
237 if (b1_rx_full(base)) in b1_get_byte()
238 return inb(base + B1_READ); in b1_get_byte()
239 printk(KERN_CRIT "b1lli(0x%x): rx not full after 1 second\n", base); in b1_get_byte()
[all …]
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| /drivers/net/ethernet/broadcom/bnx2x/ |
| D | bnx2x_fw_defs.h | 15 #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base)
17 (IRO[151].base + ((assertListEntry) * IRO[151].m1))
19 (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
22 (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
25 (IRO[163].base + ((funcId) * IRO[163].m1))
27 (IRO[153].base + ((funcId) * IRO[153].m1))
29 (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
31 (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
33 #define CSTORM_IGU_MODE_OFFSET (IRO[161].base)
35 (IRO[323].base + ((pfId) * IRO[323].m1))
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| /drivers/media/platform/s5p-jpeg/ |
| D | jpeg-hw-exynos4.c | 16 void exynos4_jpeg_sw_reset(void __iomem *base) in exynos4_jpeg_sw_reset() argument
20 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
22 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
24 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
25 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
29 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
32 void exynos4_jpeg_set_enc_dec_mode(void __iomem *base, unsigned int mode) in exynos4_jpeg_set_enc_dec_mode() argument
36 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
41 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
45 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
[all …]
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| /drivers/s390/block/ |
| D | dasd_ioctl.c | 46 struct dasd_device *base; in dasd_ioctl_enable() local
51 base = dasd_device_from_gendisk(bdev->bd_disk); in dasd_ioctl_enable()
52 if (!base) in dasd_ioctl_enable()
55 dasd_enable_device(base); in dasd_ioctl_enable()
59 (loff_t)get_capacity(base->block->gdp) << 9); in dasd_ioctl_enable()
61 dasd_put_device(base); in dasd_ioctl_enable()
72 struct dasd_device *base; in dasd_ioctl_disable() local
77 base = dasd_device_from_gendisk(bdev->bd_disk); in dasd_ioctl_disable()
78 if (!base) in dasd_ioctl_disable()
88 dasd_set_target_state(base, DASD_STATE_BASIC); in dasd_ioctl_disable()
[all …]
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| /drivers/phy/qualcomm/ |
| D | phy-qcom-apq8064-sata.c | 92 void __iomem *base = phy->mmio; in qcom_apq8064_sata_phy_init() local
96 writel_relaxed(0x01, base + SATA_PHY_SER_CTRL); in qcom_apq8064_sata_phy_init()
97 writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0); in qcom_apq8064_sata_phy_init()
102 writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0); in qcom_apq8064_sata_phy_init()
103 writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1); in qcom_apq8064_sata_phy_init()
104 writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0); in qcom_apq8064_sata_phy_init()
105 writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0); in qcom_apq8064_sata_phy_init()
106 writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2); in qcom_apq8064_sata_phy_init()
109 writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG); in qcom_apq8064_sata_phy_init()
110 writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG); in qcom_apq8064_sata_phy_init()
[all …]
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