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Searched refs:cg (Results 1 – 9 of 9) sorted by relevance

/drivers/gpio/
Dgpio-crystalcove.c113 static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg, in crystalcove_update_irq_mask() argument
119 if (cg->set_irq_mask) in crystalcove_update_irq_mask()
120 regmap_update_bits(cg->regmap, mirqs0, mask, mask); in crystalcove_update_irq_mask()
122 regmap_update_bits(cg->regmap, mirqs0, mask, 0); in crystalcove_update_irq_mask()
125 static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio) in crystalcove_update_irq_ctrl() argument
129 regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value); in crystalcove_update_irq_ctrl()
134 struct crystalcove_gpio *cg = gpiochip_get_data(chip); in crystalcove_gpio_dir_in() local
140 return regmap_write(cg->regmap, reg, CTLO_INPUT_SET); in crystalcove_gpio_dir_in()
146 struct crystalcove_gpio *cg = gpiochip_get_data(chip); in crystalcove_gpio_dir_out() local
152 return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value); in crystalcove_gpio_dir_out()
[all …]
/drivers/clk/mediatek/
Dclk-gate.c20 struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); in mtk_cg_bit_is_cleared() local
23 regmap_read(cg->regmap, cg->sta_ofs, &val); in mtk_cg_bit_is_cleared()
25 val &= BIT(cg->bit); in mtk_cg_bit_is_cleared()
32 struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); in mtk_cg_bit_is_set() local
35 regmap_read(cg->regmap, cg->sta_ofs, &val); in mtk_cg_bit_is_set()
37 val &= BIT(cg->bit); in mtk_cg_bit_is_set()
44 struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); in mtk_cg_set_bit() local
46 regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit)); in mtk_cg_set_bit()
51 struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); in mtk_cg_clr_bit() local
53 regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit)); in mtk_cg_clr_bit()
[all …]
/drivers/clk/
Dclk-qoriq.c79 void (*init_periph)(struct clockgen *cg);
99 static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg) in cg_out() argument
101 if (cg->info.flags & CG_LITTLE_ENDIAN) in cg_out()
107 static u32 cg_in(struct clockgen *cg, u32 __iomem *reg) in cg_in() argument
111 if (cg->info.flags & CG_LITTLE_ENDIAN) in cg_in()
432 static void __init p2041_init_periph(struct clockgen *cg) in p2041_init_periph() argument
436 reg = ioread32be(&cg->guts->rcwsr[7]); in p2041_init_periph()
439 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; in p2041_init_periph()
441 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p2041_init_periph()
444 static void __init p4080_init_periph(struct clockgen *cg) in p4080_init_periph() argument
[all …]
/drivers/clk/sunxi-ng/
Dccu_gate.c30 struct ccu_gate *cg = hw_to_ccu_gate(hw); in ccu_gate_disable() local
32 return ccu_gate_helper_disable(&cg->common, cg->enable); in ccu_gate_disable()
55 struct ccu_gate *cg = hw_to_ccu_gate(hw); in ccu_gate_enable() local
57 return ccu_gate_helper_enable(&cg->common, cg->enable); in ccu_gate_enable()
70 struct ccu_gate *cg = hw_to_ccu_gate(hw); in ccu_gate_is_enabled() local
72 return ccu_gate_helper_is_enabled(&cg->common, cg->enable); in ccu_gate_is_enabled()
78 struct ccu_gate *cg = hw_to_ccu_gate(hw); in ccu_gate_recalc_rate() local
81 if (cg->common.features & CCU_FEATURE_ALL_PREDIV) in ccu_gate_recalc_rate()
82 rate /= cg->common.prediv; in ccu_gate_recalc_rate()
90 struct ccu_gate *cg = hw_to_ccu_gate(hw); in ccu_gate_round_rate() local
[all …]
/drivers/infiniband/core/
Dcgroup.c41 return rdmacg_try_charge(&cg_obj->cg, &device->cg_device, in ib_rdmacg_try_charge()
50 rdmacg_uncharge(cg_obj->cg, &device->cg_device, in ib_rdmacg_uncharge()
/drivers/video/fbdev/
Dsimplefb.c49 u32 cg = green >> (16 - info->var.green.length); in simplefb_setcolreg() local
57 (cg << info->var.green.offset) | in simplefb_setcolreg()
Doffb.c104 u32 cg = green >> (16 - info->var.green.length); in offb_setcolreg() local
112 (cg << info->var.green.offset) | in offb_setcolreg()
/drivers/clk/tegra/
Dclk-dfll.c293 u32 cg; member
886 force_val = (req->lut_index - td->lut_safe) * coef / td->cg; in dfll_set_frequency_request()
1406 (td->cg << DFLL_PARAMS_CG_PARAM_SHIFT) | in dfll_set_default_params()
1853 ok &= read_dt_param(td, "nvidia,cg", &td->cg); in dfll_fetch_common_params()
/drivers/staging/media/ipu3/include/
Dintel-ipu3.h646 __u32 cg:5; member