Searched refs:clk_divider_ops (Results 1 – 25 of 27) sorted by relevance
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| /drivers/clk/st/ |
| D | clk-flexgen.c | 142 mid_rate = clk_divider_ops.recalc_rate(pdiv_hw, parent_rate); in flexgen_recalc_rate()
144 return clk_divider_ops.recalc_rate(fdiv_hw, mid_rate); in flexgen_recalc_rate()
177 clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate); in flexgen_set_rate()
178 ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div); in flexgen_set_rate()
180 clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate); in flexgen_set_rate()
181 ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div); in flexgen_set_rate()
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| D | clkgen-pll.c | 674 &div->hw, &clk_divider_ops, in clkgen_odf_register()
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| /drivers/clk/ |
| D | clk-divider.c | 453 const struct clk_ops clk_divider_ops = { variable
458 EXPORT_SYMBOL_GPL(clk_divider_ops);
493 init.ops = &clk_divider_ops; in _register_divider()
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| D | clk-stm32h7.c | 396 gcfg->div->ops : &clk_divider_ops; in get_cfg_composite_div()
845 return clk_divider_ops.recalc_rate(hw, parent_rate); in odf_divider_recalc_rate()
851 return clk_divider_ops.round_rate(hw, rate, prate); in odf_divider_round_rate()
868 ret = clk_divider_ops.set_rate(hw, rate, parent_rate); in odf_divider_set_rate()
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| D | clk-stm32f4.c | 709 return clk_divider_ops.recalc_rate(hw, parent_rate); in stm32f4_pll_div_recalc_rate()
715 return clk_divider_ops.round_rate(hw, rate, prate); in stm32f4_pll_div_round_rate()
731 ret = clk_divider_ops.set_rate(hw, rate, parent_rate); in stm32f4_pll_div_set_rate()
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| /drivers/clk/sunxi/ |
| D | clk-sun8i-mbus.c | 79 &div->hw, &clk_divider_ops, in sun8i_a23_mbus_setup()
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| D | clk-a10-ve.c | 122 &div->hw, &clk_divider_ops, in sun4i_ve_clk_setup()
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| D | clk-sun4i-display.c | 161 data->has_div ? &clk_divider_ops : NULL, in sun4i_a10_display_init()
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| D | clk-sunxi.c | 1073 rate_ops = &clk_divider_ops; in sunxi_divs_clk_setup()
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| /drivers/clk/mxs/ |
| D | clk-div.c | 96 div->ops = &clk_divider_ops; in mxs_clk_div()
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| /drivers/clk/imx/ |
| D | clk-fixup-div.c | 115 fixup_div->ops = &clk_divider_ops; in imx_clk_hw_fixup_divider()
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| D | clk-busy.c | 95 busy->div_ops = &clk_divider_ops; in imx_clk_hw_busy_divider()
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| D | clk-divider-gate.c | 70 return clk_divider_ops.round_rate(hw, rate, prate); in clk_divider_round_rate()
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| /drivers/clk/zte/ |
| D | clk.h | 133 &clk_divider_ops, \
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| /drivers/clk/davinci/ |
| D | pll.c | 242 const struct clk_ops *divider_ops = &clk_divider_ops; in davinci_pll_div_register()
619 ÷r->hw, &clk_divider_ops, in davinci_pll_obsclk_register()
681 const struct clk_ops *divider_ops = &clk_divider_ops; in davinci_pll_sysclk_register()
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| /drivers/clk/mediatek/ |
| D | clk-mtk.c | 213 div_ops = &clk_divider_ops; in mtk_clk_register_composite()
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| /drivers/clk/renesas/ |
| D | rcar-gen2-cpg.c | 235 &div->hw, &clk_divider_ops, in cpg_adsp_clk_register()
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| D | clk-rcar-gen2.c | 236 &div->hw, &clk_divider_ops, in cpg_adsp_clk_register()
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| D | rcar-gen3-cpg.c | 466 &rpc->div.hw, &clk_divider_ops, in cpg_rpc_clk_register()
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| /drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-meson8b.c | 161 &clk_divider_ops, in meson8b_init_rgmii_tx_clk()
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| /drivers/clk/nxp/ |
| D | clk-lpc18xx-cgu.c | 549 &clk->div.hw, &clk_divider_ops, in lpc18xx_cgu_register_div()
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| /drivers/mmc/host/ |
| D | meson-mx-sdio.c | 618 init.ops = &clk_divider_ops; in meson_mx_mmc_register_clks()
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| /drivers/clk/rockchip/ |
| D | clk.c | 100 : &clk_divider_ops; in rockchip_clk_register_branch()
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| /drivers/clk/bcm/ |
| D | clk-bcm2835.c | 795 return clk_divider_ops.round_rate(hw, rate, parent_rate); in bcm2835_pll_divider_round_rate()
801 return clk_divider_ops.recalc_rate(hw, parent_rate); in bcm2835_pll_divider_get_rate()
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| /drivers/iio/adc/ |
| D | meson_saradc.c | 664 init.ops = &clk_divider_ops; in meson_sar_adc_clk_init()
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