1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * rcar_gen2 Core CPG Clocks
4 *
5 * Copyright (C) 2013 Ideas On Board SPRL
6 *
7 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
8 */
9
10 #include <linux/clk-provider.h>
11 #include <linux/clk/renesas.h>
12 #include <linux/init.h>
13 #include <linux/io.h>
14 #include <linux/kernel.h>
15 #include <linux/math64.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/slab.h>
19 #include <linux/spinlock.h>
20 #include <linux/soc/renesas/rcar-rst.h>
21
22 struct rcar_gen2_cpg {
23 struct clk_onecell_data data;
24 spinlock_t lock;
25 void __iomem *reg;
26 };
27
28 #define CPG_FRQCRB 0x00000004
29 #define CPG_FRQCRB_KICK BIT(31)
30 #define CPG_SDCKCR 0x00000074
31 #define CPG_PLL0CR 0x000000d8
32 #define CPG_FRQCRC 0x000000e0
33 #define CPG_FRQCRC_ZFC_MASK (0x1f << 8)
34 #define CPG_FRQCRC_ZFC_SHIFT 8
35 #define CPG_ADSPCKCR 0x0000025c
36 #define CPG_RCANCKCR 0x00000270
37
38 /* -----------------------------------------------------------------------------
39 * Z Clock
40 *
41 * Traits of this clock:
42 * prepare - clk_prepare only ensures that parents are prepared
43 * enable - clk_enable only ensures that parents are enabled
44 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
45 * parent - fixed parent. No clk_set_parent support
46 */
47
48 struct cpg_z_clk {
49 struct clk_hw hw;
50 void __iomem *reg;
51 void __iomem *kick_reg;
52 };
53
54 #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
55
cpg_z_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)56 static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
57 unsigned long parent_rate)
58 {
59 struct cpg_z_clk *zclk = to_z_clk(hw);
60 unsigned int mult;
61 unsigned int val;
62
63 val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT;
64 mult = 32 - val;
65
66 return div_u64((u64)parent_rate * mult, 32);
67 }
68
cpg_z_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)69 static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
70 unsigned long *parent_rate)
71 {
72 unsigned long prate = *parent_rate;
73 unsigned int mult;
74
75 if (!prate)
76 prate = 1;
77
78 mult = div_u64((u64)rate * 32, prate);
79 mult = clamp(mult, 1U, 32U);
80
81 return *parent_rate / 32 * mult;
82 }
83
cpg_z_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)84 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
85 unsigned long parent_rate)
86 {
87 struct cpg_z_clk *zclk = to_z_clk(hw);
88 unsigned int mult;
89 u32 val, kick;
90 unsigned int i;
91
92 mult = div_u64((u64)rate * 32, parent_rate);
93 mult = clamp(mult, 1U, 32U);
94
95 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
96 return -EBUSY;
97
98 val = readl(zclk->reg);
99 val &= ~CPG_FRQCRC_ZFC_MASK;
100 val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
101 writel(val, zclk->reg);
102
103 /*
104 * Set KICK bit in FRQCRB to update hardware setting and wait for
105 * clock change completion.
106 */
107 kick = readl(zclk->kick_reg);
108 kick |= CPG_FRQCRB_KICK;
109 writel(kick, zclk->kick_reg);
110
111 /*
112 * Note: There is no HW information about the worst case latency.
113 *
114 * Using experimental measurements, it seems that no more than
115 * ~10 iterations are needed, independently of the CPU rate.
116 * Since this value might be dependent on external xtal rate, pll1
117 * rate or even the other emulation clocks rate, use 1000 as a
118 * "super" safe value.
119 */
120 for (i = 1000; i; i--) {
121 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
122 return 0;
123
124 cpu_relax();
125 }
126
127 return -ETIMEDOUT;
128 }
129
130 static const struct clk_ops cpg_z_clk_ops = {
131 .recalc_rate = cpg_z_clk_recalc_rate,
132 .round_rate = cpg_z_clk_round_rate,
133 .set_rate = cpg_z_clk_set_rate,
134 };
135
cpg_z_clk_register(struct rcar_gen2_cpg * cpg)136 static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg)
137 {
138 static const char *parent_name = "pll0";
139 struct clk_init_data init;
140 struct cpg_z_clk *zclk;
141 struct clk *clk;
142
143 zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
144 if (!zclk)
145 return ERR_PTR(-ENOMEM);
146
147 init.name = "z";
148 init.ops = &cpg_z_clk_ops;
149 init.flags = 0;
150 init.parent_names = &parent_name;
151 init.num_parents = 1;
152
153 zclk->reg = cpg->reg + CPG_FRQCRC;
154 zclk->kick_reg = cpg->reg + CPG_FRQCRB;
155 zclk->hw.init = &init;
156
157 clk = clk_register(NULL, &zclk->hw);
158 if (IS_ERR(clk))
159 kfree(zclk);
160
161 return clk;
162 }
163
cpg_rcan_clk_register(struct rcar_gen2_cpg * cpg,struct device_node * np)164 static struct clk * __init cpg_rcan_clk_register(struct rcar_gen2_cpg *cpg,
165 struct device_node *np)
166 {
167 const char *parent_name = of_clk_get_parent_name(np, 1);
168 struct clk_fixed_factor *fixed;
169 struct clk_gate *gate;
170 struct clk *clk;
171
172 fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
173 if (!fixed)
174 return ERR_PTR(-ENOMEM);
175
176 fixed->mult = 1;
177 fixed->div = 6;
178
179 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
180 if (!gate) {
181 kfree(fixed);
182 return ERR_PTR(-ENOMEM);
183 }
184
185 gate->reg = cpg->reg + CPG_RCANCKCR;
186 gate->bit_idx = 8;
187 gate->flags = CLK_GATE_SET_TO_DISABLE;
188 gate->lock = &cpg->lock;
189
190 clk = clk_register_composite(NULL, "rcan", &parent_name, 1, NULL, NULL,
191 &fixed->hw, &clk_fixed_factor_ops,
192 &gate->hw, &clk_gate_ops, 0);
193 if (IS_ERR(clk)) {
194 kfree(gate);
195 kfree(fixed);
196 }
197
198 return clk;
199 }
200
201 /* ADSP divisors */
202 static const struct clk_div_table cpg_adsp_div_table[] = {
203 { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 },
204 { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
205 { 10, 36 }, { 11, 48 }, { 0, 0 },
206 };
207
cpg_adsp_clk_register(struct rcar_gen2_cpg * cpg)208 static struct clk * __init cpg_adsp_clk_register(struct rcar_gen2_cpg *cpg)
209 {
210 const char *parent_name = "pll1";
211 struct clk_divider *div;
212 struct clk_gate *gate;
213 struct clk *clk;
214
215 div = kzalloc(sizeof(*div), GFP_KERNEL);
216 if (!div)
217 return ERR_PTR(-ENOMEM);
218
219 div->reg = cpg->reg + CPG_ADSPCKCR;
220 div->width = 4;
221 div->table = cpg_adsp_div_table;
222 div->lock = &cpg->lock;
223
224 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
225 if (!gate) {
226 kfree(div);
227 return ERR_PTR(-ENOMEM);
228 }
229
230 gate->reg = cpg->reg + CPG_ADSPCKCR;
231 gate->bit_idx = 8;
232 gate->flags = CLK_GATE_SET_TO_DISABLE;
233 gate->lock = &cpg->lock;
234
235 clk = clk_register_composite(NULL, "adsp", &parent_name, 1, NULL, NULL,
236 &div->hw, &clk_divider_ops,
237 &gate->hw, &clk_gate_ops, 0);
238 if (IS_ERR(clk)) {
239 kfree(gate);
240 kfree(div);
241 }
242
243 return clk;
244 }
245
246 /* -----------------------------------------------------------------------------
247 * CPG Clock Data
248 */
249
250 /*
251 * MD EXTAL PLL0 PLL1 PLL3
252 * 14 13 19 (MHz) *1 *1
253 *---------------------------------------------------
254 * 0 0 0 15 x 1 x172/2 x208/2 x106
255 * 0 0 1 15 x 1 x172/2 x208/2 x88
256 * 0 1 0 20 x 1 x130/2 x156/2 x80
257 * 0 1 1 20 x 1 x130/2 x156/2 x66
258 * 1 0 0 26 / 2 x200/2 x240/2 x122
259 * 1 0 1 26 / 2 x200/2 x240/2 x102
260 * 1 1 0 30 / 2 x172/2 x208/2 x106
261 * 1 1 1 30 / 2 x172/2 x208/2 x88
262 *
263 * *1 : Table 7.6 indicates VCO output (PLLx = VCO/2)
264 */
265 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
266 (((md) & BIT(13)) >> 12) | \
267 (((md) & BIT(19)) >> 19))
268 struct cpg_pll_config {
269 unsigned int extal_div;
270 unsigned int pll1_mult;
271 unsigned int pll3_mult;
272 unsigned int pll0_mult; /* For R-Car V2H and E2 only */
273 };
274
275 static const struct cpg_pll_config cpg_pll_configs[8] __initconst = {
276 { 1, 208, 106, 200 }, { 1, 208, 88, 200 },
277 { 1, 156, 80, 150 }, { 1, 156, 66, 150 },
278 { 2, 240, 122, 230 }, { 2, 240, 102, 230 },
279 { 2, 208, 106, 200 }, { 2, 208, 88, 200 },
280 };
281
282 /* SDHI divisors */
283 static const struct clk_div_table cpg_sdh_div_table[] = {
284 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
285 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
286 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
287 };
288
289 static const struct clk_div_table cpg_sd01_div_table[] = {
290 { 4, 8 },
291 { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
292 { 10, 36 }, { 11, 48 }, { 12, 10 }, { 0, 0 },
293 };
294
295 /* -----------------------------------------------------------------------------
296 * Initialization
297 */
298
299 static u32 cpg_mode __initdata;
300
301 static const char * const pll0_mult_match[] = {
302 "renesas,r8a7792-cpg-clocks",
303 "renesas,r8a7794-cpg-clocks",
304 NULL
305 };
306
307 static struct clk * __init
rcar_gen2_cpg_register_clock(struct device_node * np,struct rcar_gen2_cpg * cpg,const struct cpg_pll_config * config,const char * name)308 rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
309 const struct cpg_pll_config *config,
310 const char *name)
311 {
312 const struct clk_div_table *table = NULL;
313 const char *parent_name;
314 unsigned int shift;
315 unsigned int mult = 1;
316 unsigned int div = 1;
317
318 if (!strcmp(name, "main")) {
319 parent_name = of_clk_get_parent_name(np, 0);
320 div = config->extal_div;
321 } else if (!strcmp(name, "pll0")) {
322 /* PLL0 is a configurable multiplier clock. Register it as a
323 * fixed factor clock for now as there's no generic multiplier
324 * clock implementation and we currently have no need to change
325 * the multiplier value.
326 */
327 if (of_device_compatible_match(np, pll0_mult_match)) {
328 /* R-Car V2H and E2 do not have PLL0CR */
329 mult = config->pll0_mult;
330 div = 3;
331 } else {
332 u32 value = readl(cpg->reg + CPG_PLL0CR);
333 mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
334 }
335 parent_name = "main";
336 } else if (!strcmp(name, "pll1")) {
337 parent_name = "main";
338 mult = config->pll1_mult / 2;
339 } else if (!strcmp(name, "pll3")) {
340 parent_name = "main";
341 mult = config->pll3_mult;
342 } else if (!strcmp(name, "lb")) {
343 parent_name = "pll1";
344 div = cpg_mode & BIT(18) ? 36 : 24;
345 } else if (!strcmp(name, "qspi")) {
346 parent_name = "pll1_div2";
347 div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2)
348 ? 8 : 10;
349 } else if (!strcmp(name, "sdh")) {
350 parent_name = "pll1";
351 table = cpg_sdh_div_table;
352 shift = 8;
353 } else if (!strcmp(name, "sd0")) {
354 parent_name = "pll1";
355 table = cpg_sd01_div_table;
356 shift = 4;
357 } else if (!strcmp(name, "sd1")) {
358 parent_name = "pll1";
359 table = cpg_sd01_div_table;
360 shift = 0;
361 } else if (!strcmp(name, "z")) {
362 return cpg_z_clk_register(cpg);
363 } else if (!strcmp(name, "rcan")) {
364 return cpg_rcan_clk_register(cpg, np);
365 } else if (!strcmp(name, "adsp")) {
366 return cpg_adsp_clk_register(cpg);
367 } else {
368 return ERR_PTR(-EINVAL);
369 }
370
371 if (!table)
372 return clk_register_fixed_factor(NULL, name, parent_name, 0,
373 mult, div);
374 else
375 return clk_register_divider_table(NULL, name, parent_name, 0,
376 cpg->reg + CPG_SDCKCR, shift,
377 4, 0, table, &cpg->lock);
378 }
379
380 /*
381 * Reset register definitions.
382 */
383 #define MODEMR 0xe6160060
384
rcar_gen2_read_mode_pins(void)385 static u32 __init rcar_gen2_read_mode_pins(void)
386 {
387 void __iomem *modemr = ioremap_nocache(MODEMR, 4);
388 u32 mode;
389
390 BUG_ON(!modemr);
391 mode = ioread32(modemr);
392 iounmap(modemr);
393
394 return mode;
395 }
396
rcar_gen2_cpg_clocks_init(struct device_node * np)397 static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
398 {
399 const struct cpg_pll_config *config;
400 struct rcar_gen2_cpg *cpg;
401 struct clk **clks;
402 unsigned int i;
403 int num_clks;
404
405 if (rcar_rst_read_mode_pins(&cpg_mode)) {
406 /* Backward-compatibility with old DT */
407 pr_warn("%pOF: failed to obtain mode pins from RST\n", np);
408 cpg_mode = rcar_gen2_read_mode_pins();
409 }
410
411 num_clks = of_property_count_strings(np, "clock-output-names");
412 if (num_clks < 0) {
413 pr_err("%s: failed to count clocks\n", __func__);
414 return;
415 }
416
417 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
418 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
419 if (cpg == NULL || clks == NULL) {
420 /* We're leaking memory on purpose, there's no point in cleaning
421 * up as the system won't boot anyway.
422 */
423 return;
424 }
425
426 spin_lock_init(&cpg->lock);
427
428 cpg->data.clks = clks;
429 cpg->data.clk_num = num_clks;
430
431 cpg->reg = of_iomap(np, 0);
432 if (WARN_ON(cpg->reg == NULL))
433 return;
434
435 config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
436
437 for (i = 0; i < num_clks; ++i) {
438 const char *name;
439 struct clk *clk;
440
441 of_property_read_string_index(np, "clock-output-names", i,
442 &name);
443
444 clk = rcar_gen2_cpg_register_clock(np, cpg, config, name);
445 if (IS_ERR(clk))
446 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
447 __func__, np, name, PTR_ERR(clk));
448 else
449 cpg->data.clks[i] = clk;
450 }
451
452 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
453
454 cpg_mstp_add_clk_domain(np);
455 }
456 CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
457 rcar_gen2_cpg_clocks_init);
458