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/drivers/net/ethernet/mellanox/mlx5/core/lib/
Dclock.c71 struct mlx5_clock *clock = container_of(cc, struct mlx5_clock, cycles); in read_internal_timer() local
72 struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, in read_internal_timer()
73 clock); in read_internal_timer()
81 struct mlx5_clock *clock = &mdev->clock; in mlx5_update_clock_info_page() local
91 clock_info->cycles = clock->tc.cycle_last; in mlx5_update_clock_info_page()
92 clock_info->mult = clock->cycles.mult; in mlx5_update_clock_info_page()
93 clock_info->nsec = clock->tc.nsec; in mlx5_update_clock_info_page()
94 clock_info->frac = clock->tc.frac; in mlx5_update_clock_info_page()
104 struct mlx5_clock *clock = container_of(pps_info, struct mlx5_clock, in mlx5_pps_out() local
106 struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, in mlx5_pps_out()
[all …]
Dclock.h42 return mdev->clock.ptp ? ptp_clock_index(mdev->clock.ptp) : -1; in mlx5_clock_get_ptp_index()
45 static inline ktime_t mlx5_timecounter_cyc2time(struct mlx5_clock *clock, in mlx5_timecounter_cyc2time() argument
52 seq = read_seqbegin(&clock->lock); in mlx5_timecounter_cyc2time()
53 nsec = timecounter_cyc2time(&clock->tc, timestamp); in mlx5_timecounter_cyc2time()
54 } while (read_seqretry(&clock->lock, seq)); in mlx5_timecounter_cyc2time()
67 static inline ktime_t mlx5_timecounter_cyc2time(struct mlx5_clock *clock, in mlx5_timecounter_cyc2time() argument
/drivers/clk/renesas/
Dclk-div6.c50 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_enable() local
53 val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP)) in cpg_div6_clock_enable()
54 | CPG_DIV6_DIV(clock->div - 1); in cpg_div6_clock_enable()
55 writel(val, clock->reg); in cpg_div6_clock_enable()
62 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_disable() local
65 val = readl(clock->reg); in cpg_div6_clock_disable()
75 writel(val, clock->reg); in cpg_div6_clock_disable()
80 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_is_enabled() local
82 return !(readl(clock->reg) & CPG_DIV6_CKSTP); in cpg_div6_clock_is_enabled()
88 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_recalc_rate() local
[all …]
DKconfig4 bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
35 bool "Legacy DT clock support"
47 bool "Emma Mobile EV2 clock support" if COMPILE_TEST
50 bool "RZ/A1H clock support" if COMPILE_TEST
54 bool "RZ/A2 clock support" if COMPILE_TEST
58 bool "R-Mobile APE6 clock support" if COMPILE_TEST
63 bool "R-Mobile A1 clock support" if COMPILE_TEST
68 bool "RZ/G1M clock support" if COMPILE_TEST
72 bool "RZ/G1E clock support" if COMPILE_TEST
76 bool "RZ/G1C clock support" if COMPILE_TEST
[all …]
Drcar-gen3-cpg.c280 struct sd_clock *clock = to_sd_clock(hw); in cpg_sd_clock_enable() local
282 cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK, in cpg_sd_clock_enable()
283 clock->div_table[clock->cur_div_idx].val & in cpg_sd_clock_enable()
291 struct sd_clock *clock = to_sd_clock(hw); in cpg_sd_clock_disable() local
293 cpg_reg_modify(clock->csn.reg, 0, CPG_SD_STP_MASK); in cpg_sd_clock_disable()
298 struct sd_clock *clock = to_sd_clock(hw); in cpg_sd_clock_is_enabled() local
300 return !(readl(clock->csn.reg) & CPG_SD_STP_MASK); in cpg_sd_clock_is_enabled()
306 struct sd_clock *clock = to_sd_clock(hw); in cpg_sd_clock_recalc_rate() local
309 clock->div_table[clock->cur_div_idx].div); in cpg_sd_clock_recalc_rate()
312 static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock, in cpg_sd_clock_calc_div() argument
[all …]
Dclk-mstp.c77 struct mstp_clock *clock = to_mstp_clock(hw); in cpg_mstp_clock_endisable() local
78 struct mstp_clock_group *group = clock->group; in cpg_mstp_clock_endisable()
79 u32 bitmask = BIT(clock->bit_index); in cpg_mstp_clock_endisable()
112 group->smstpcr, clock->bit_index); in cpg_mstp_clock_endisable()
131 struct mstp_clock *clock = to_mstp_clock(hw); in cpg_mstp_clock_is_enabled() local
132 struct mstp_clock_group *group = clock->group; in cpg_mstp_clock_is_enabled()
140 return !(value & BIT(clock->bit_index)); in cpg_mstp_clock_is_enabled()
154 struct mstp_clock *clock; in cpg_mstp_clock_register() local
157 clock = kzalloc(sizeof(*clock), GFP_KERNEL); in cpg_mstp_clock_register()
158 if (!clock) in cpg_mstp_clock_register()
[all …]
/drivers/net/ethernet/cavium/common/
Dcavium_ptp.c92 struct cavium_ptp *clock = in cavium_ptp_adjfine() local
119 comp = ((u64)1000000000ull << 32) / clock->clock_rate; in cavium_ptp_adjfine()
125 spin_lock_irqsave(&clock->spin_lock, flags); in cavium_ptp_adjfine()
126 writeq(comp, clock->reg_base + PTP_CLOCK_COMP); in cavium_ptp_adjfine()
127 spin_unlock_irqrestore(&clock->spin_lock, flags); in cavium_ptp_adjfine()
139 struct cavium_ptp *clock = in cavium_ptp_adjtime() local
143 spin_lock_irqsave(&clock->spin_lock, flags); in cavium_ptp_adjtime()
144 timecounter_adjtime(&clock->time_counter, delta); in cavium_ptp_adjtime()
145 spin_unlock_irqrestore(&clock->spin_lock, flags); in cavium_ptp_adjtime()
161 struct cavium_ptp *clock = in cavium_ptp_gettime() local
[all …]
/drivers/soc/fsl/qe/
Ducc.c119 int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock, in ucc_set_qe_mux_rxtx() argument
139 switch (clock) { in ucc_set_qe_mux_rxtx()
154 switch (clock) { in ucc_set_qe_mux_rxtx()
169 switch (clock) { in ucc_set_qe_mux_rxtx()
185 switch (clock) { in ucc_set_qe_mux_rxtx()
216 static int ucc_get_tdm_common_clk(u32 tdm_num, enum qe_clock clock) in ucc_get_tdm_common_clk() argument
231 switch (clock) { in ucc_get_tdm_common_clk()
252 switch (clock) { in ucc_get_tdm_common_clk()
276 static int ucc_get_tdm_rx_clk(u32 tdm_num, enum qe_clock clock) in ucc_get_tdm_rx_clk() argument
282 switch (clock) { in ucc_get_tdm_rx_clk()
[all …]
/drivers/gpu/drm/gma500/
Dcdv_intel_display.c213 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select) in cdv_dpll_set_clock_cdv() argument
271 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
287 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
289 if (clock->vco < 2250000) { in cdv_dpll_set_clock_cdv()
292 } else if (clock->vco < 2750000) { in cdv_dpll_set_clock_cdv()
295 } else if (clock->vco < 3300000) { in cdv_dpll_set_clock_cdv()
311 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); in cdv_dpll_set_clock_cdv()
312 switch (clock->p2) { in cdv_dpll_set_clock_cdv()
326 DRM_ERROR("Bad P2 clock: %d\n", clock->p2); in cdv_dpll_set_clock_cdv()
392 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock) in cdv_intel_clock() argument
[all …]
Doaktrail_crtc.c111 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) in mrst_lvds_clock() argument
113 clock->dot = (refclk * clock->m) / (14 * clock->p1); in mrst_lvds_clock()
116 static void mrst_print_pll(struct gma_clock_t *clock) in mrst_print_pll() argument
119 clock->dot, clock->m, clock->m1, clock->m2, clock->n, in mrst_print_pll()
120 clock->p1, clock->p2); in mrst_print_pll()
127 struct gma_clock_t clock; in mrst_sdvo_find_best_pll() local
132 memset(&clock, 0, sizeof(clock)); in mrst_sdvo_find_best_pll()
134 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) { in mrst_sdvo_find_best_pll()
135 for (clock.n = limit->n.min; clock.n <= limit->n.max; in mrst_sdvo_find_best_pll()
136 clock.n++) { in mrst_sdvo_find_best_pll()
[all …]
Dpsb_intel_display.c66 static void psb_intel_clock(int refclk, struct gma_clock_t *clock) in psb_intel_clock() argument
68 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in psb_intel_clock()
69 clock->p = clock->p1 * clock->p2; in psb_intel_clock()
70 clock->vco = refclk * clock->m / (clock->n + 2); in psb_intel_clock()
71 clock->dot = clock->vco / clock->p; in psb_intel_clock()
104 struct gma_clock_t clock; in psb_intel_crtc_mode_set() local
142 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, in psb_intel_crtc_mode_set()
143 &clock); in psb_intel_crtc_mode_set()
146 adjusted_mode->clock, clock.dot); in psb_intel_crtc_mode_set()
150 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; in psb_intel_crtc_mode_set()
[all …]
Dgma_display.c670 struct gma_clock_t *clock) in gma_pll_is_valid() argument
672 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) in gma_pll_is_valid()
674 if (clock->p < limit->p.min || limit->p.max < clock->p) in gma_pll_is_valid()
676 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) in gma_pll_is_valid()
678 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) in gma_pll_is_valid()
681 if (clock->m1 <= clock->m2 && clock->m1 != 0) in gma_pll_is_valid()
683 if (clock->m < limit->m.min || limit->m.max < clock->m) in gma_pll_is_valid()
685 if (clock->n < limit->n.min || limit->n.max < clock->n) in gma_pll_is_valid()
687 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) in gma_pll_is_valid()
693 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) in gma_pll_is_valid()
[all …]
/drivers/net/phy/
Ddp83640.c99 struct dp83640_clock *clock; member
222 if (dp83640->clock->page != page) { in ext_read()
224 dp83640->clock->page = page; in ext_read()
237 if (dp83640->clock->page != page) { in ext_write()
239 dp83640->clock->page = page; in ext_write()
294 static int periodic_output(struct dp83640_clock *clock, in periodic_output() argument
298 struct dp83640_private *dp83640 = clock->chosen; in periodic_output()
304 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, in periodic_output()
322 mutex_lock(&clock->extreg_lock); in periodic_output()
325 mutex_unlock(&clock->extreg_lock); in periodic_output()
[all …]
/drivers/video/fbdev/via/
Dvia_clock.c282 void via_clock_init(struct via_clock *clock, int gfx_chip) in via_clock_init() argument
287 clock->set_primary_clock_state = dummy_set_clock_state; in via_clock_init()
288 clock->set_primary_clock_source = dummy_set_clock_source; in via_clock_init()
289 clock->set_primary_pll_state = dummy_set_pll_state; in via_clock_init()
290 clock->set_primary_pll = cle266_set_primary_pll; in via_clock_init()
292 clock->set_secondary_clock_state = dummy_set_clock_state; in via_clock_init()
293 clock->set_secondary_clock_source = dummy_set_clock_source; in via_clock_init()
294 clock->set_secondary_pll_state = dummy_set_pll_state; in via_clock_init()
295 clock->set_secondary_pll = cle266_set_secondary_pll; in via_clock_init()
297 clock->set_engine_pll_state = dummy_set_pll_state; in via_clock_init()
[all …]
/drivers/net/ethernet/mellanox/mlxsw/
Dspectrum_ptp.c73 static u64 __mlxsw_sp1_ptp_read_frc(struct mlxsw_sp_ptp_clock *clock, in __mlxsw_sp1_ptp_read_frc() argument
76 struct mlxsw_core *mlxsw_core = clock->core; in __mlxsw_sp1_ptp_read_frc()
97 struct mlxsw_sp_ptp_clock *clock = in mlxsw_sp1_ptp_read_frc() local
100 return __mlxsw_sp1_ptp_read_frc(clock, NULL) & cc->mask; in mlxsw_sp1_ptp_read_frc()
104 mlxsw_sp1_ptp_phc_adjfreq(struct mlxsw_sp_ptp_clock *clock, int freq_adj) in mlxsw_sp1_ptp_phc_adjfreq() argument
106 struct mlxsw_core *mlxsw_core = clock->core; in mlxsw_sp1_ptp_phc_adjfreq()
125 mlxsw_sp1_ptp_phc_settime(struct mlxsw_sp_ptp_clock *clock, u64 nsec) in mlxsw_sp1_ptp_phc_settime() argument
127 struct mlxsw_core *mlxsw_core = clock->core; in mlxsw_sp1_ptp_phc_settime()
136 spin_lock_bh(&clock->lock); in mlxsw_sp1_ptp_phc_settime()
137 cycles = mlxsw_sp1_ptp_ns2cycles(&clock->tc, next_sec_in_nsec); in mlxsw_sp1_ptp_phc_settime()
[all …]
/drivers/clk/bcm/
DKconfig3 bool "Broadcom BCM2835 clock support"
8 Enable common clock framework support for Broadcom BCM2835
12 bool "Broadcom BCM63xx clock support"
17 Enable common clock framework support for Broadcom BCM63xx DSL SoCs
21 bool "Broadcom BCM63xx gated clock support"
25 Enable common clock framework support for Broadcom BCM63xx DSL SoCs
29 bool "Broadcom Kona CCU clock support"
33 Enable common clock framework support for Broadcom SoCs
34 using "Kona" style clock control units, including those
40 Enable common clock framework support for Broadcom SoCs
[all …]
/drivers/clk/ti/
Dadpll.c213 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock, in ti_adpll_setup_clock() argument
221 d->clocks[index].clk = clock; in ti_adpll_setup_clock()
231 cl = clkdev_create(clock, con_id, NULL); in ti_adpll_setup_clock()
242 d->outputs.clks[output_index] = clock; in ti_adpll_setup_clock()
258 struct clk *clock; in ti_adpll_init_divider() local
265 clock = clk_register_divider(d->dev, child_name, parent_name, 0, in ti_adpll_init_divider()
268 if (IS_ERR(clock)) { in ti_adpll_init_divider()
270 name, PTR_ERR(clock)); in ti_adpll_init_divider()
271 return PTR_ERR(clock); in ti_adpll_init_divider()
274 return ti_adpll_setup_clock(d, clock, index, output_index, child_name, in ti_adpll_init_divider()
[all …]
/drivers/media/platform/qcom/camss/
Dcamss-csiphy.c114 struct camss_clock *clock = &csiphy->clock[i]; in csiphy_set_clock_rates() local
116 if (!strcmp(clock->name, "csiphy0_timer") || in csiphy_set_clock_rates()
117 !strcmp(clock->name, "csiphy1_timer") || in csiphy_set_clock_rates()
118 !strcmp(clock->name, "csiphy2_timer")) { in csiphy_set_clock_rates()
128 for (j = 0; j < clock->nfreqs; j++) in csiphy_set_clock_rates()
129 if (min_rate < clock->freq[j]) in csiphy_set_clock_rates()
132 if (j == clock->nfreqs) { in csiphy_set_clock_rates()
141 j = clock->nfreqs - 1; in csiphy_set_clock_rates()
143 round_rate = clk_round_rate(clock->clk, clock->freq[j]); in csiphy_set_clock_rates()
152 ret = clk_set_rate(clock->clk, csiphy->timer_clk_rate); in csiphy_set_clock_rates()
[all …]
/drivers/ptp/
DKconfig3 # PTP clock support configuration
6 menu "PTP clock support"
9 tristate "PTP clock support"
23 devices. If you want to use a PTP clock, then you should
24 also enable at least one clock driver as well.
30 tristate "Broadcom DTE as PTP clock"
37 (DTE) in the Broadcom SoC's as a PTP clock.
39 The clock can be used in both wired and wireless networks
46 tristate "Freescale QorIQ 1588 timer as PTP clock"
52 timer as a PTP clock. This clock is only useful if your PTP
[all …]
/drivers/gpu/drm/mgag200/
Dmgag200_mode.c102 static int mga_g200se_set_plls(struct mga_device *mdev, long clock) in mga_g200se_set_plls() argument
121 permitteddelta = clock * 5 / 1000; in mga_g200se_set_plls()
124 if (clock * testp > vcomax) in mga_g200se_set_plls()
126 if (clock * testp < vcomin) in mga_g200se_set_plls()
133 if (computed > clock) in mga_g200se_set_plls()
134 tmpdelta = computed - clock; in mga_g200se_set_plls()
136 tmpdelta = clock - computed; in mga_g200se_set_plls()
154 if (clock < 25000) in mga_g200se_set_plls()
155 clock = 25000; in mga_g200se_set_plls()
157 clock = clock * 2; in mga_g200se_set_plls()
[all …]
/drivers/clk/zynqmp/
Dclkc.c134 static struct zynqmp_clock *clock; variable
150 return clock[clk_id].valid; in zynqmp_is_valid_clock()
166 strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN); in zynqmp_get_clock_name()
186 *type = clock[clk_id].type; in zynqmp_get_clock_type()
423 ret = zynqmp_pm_clock_get_topology(clock[clk_id].clk_id, j, in zynqmp_clock_get_topology()
490 ret = zynqmp_pm_clock_get_parents(clock[clk_id].clk_id, j, in zynqmp_clock_get_parents()
518 u32 total_parents = clock[clk_id].num_parents; in zynqmp_get_parent_list()
522 clk_nodes = clock[clk_id].node; in zynqmp_get_parent_list()
523 parents = clock[clk_id].parent; in zynqmp_get_parent_list()
565 nodes = clock[clk_id].node; in zynqmp_register_clk_topology()
[all …]
/drivers/clocksource/
Dclps711x-timer.c30 static void __init clps711x_clksrc_init(struct clk *clock, void __iomem *base) in clps711x_clksrc_init() argument
32 unsigned long rate = clk_get_rate(clock); in clps711x_clksrc_init()
51 static int __init _clps711x_clkevt_init(struct clk *clock, void __iomem *base, in _clps711x_clkevt_init() argument
61 rate = clk_get_rate(clock); in _clps711x_clkevt_init()
79 struct clk *clock = of_clk_get(np, 0); in clps711x_timer_init() local
86 if (IS_ERR(clock)) in clps711x_timer_init()
87 return PTR_ERR(clock); in clps711x_timer_init()
91 clps711x_clksrc_init(clock, base); in clps711x_timer_init()
94 return _clps711x_clkevt_init(clock, base, irq); in clps711x_timer_init()
/drivers/clk/samsung/
DKconfig4 bool "Samsung Exynos clock controller support" if COMPILE_TEST
10 bool "Samsung Exynos ARMv8-family clock controller support" if COMPILE_TEST
14 tristate "Samsung Exynos AUDSS clock controller support"
18 Support for the Audio Subsystem CLKCON clock controller present
24 bool "Samsung S3C2410 clock controller support" if COMPILE_TEST
27 Build the s3c2410 clock driver based on the common clock framework.
34 Temporary symbol to build the dclk driver based on the common clock
38 bool "Samsung S3C2412 clock controller support" if COMPILE_TEST
42 bool "Samsung S3C2443 clock controller support" if COMPILE_TEST
/drivers/staging/clocking-wizard/
Ddt-binding.txt3 This binding uses the common clock binding[1]. Details about the devices can be
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13 - clocks: Handle to input clock
14 - clock-names: Tuple containing 'clk_in1' and 's_axi_aclk'
15 - clock-output-names: Names for the output clocks
21 clock-generator@40040000 {
25 clock-names = "clk_in1", "s_axi_aclk";
27 clock-output-names = "clk_out0", "clk_out1", "clk_out2",
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_afmt.c51 static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq) in amdgpu_afmt_calc_cts() argument
58 cts = clock * 1000; in amdgpu_afmt_calc_cts()
88 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock) in amdgpu_afmt_acr() argument
95 if (amdgpu_afmt_predefined_acr[i].clock == clock) in amdgpu_afmt_acr()
100 amdgpu_afmt_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000); in amdgpu_afmt_acr()
101 amdgpu_afmt_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100); in amdgpu_afmt_acr()
102 amdgpu_afmt_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000); in amdgpu_afmt_acr()

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