Searched refs:con0 (Results 1 – 4 of 4) sorted by relevance
| /drivers/clk/samsung/ |
| D | clk-pll.c | 439 u32 con0, con1; in samsung_pll45xx_set_rate() local
450 con0 = readl_relaxed(pll->con_reg); in samsung_pll45xx_set_rate()
453 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) { in samsung_pll45xx_set_rate()
455 con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT); in samsung_pll45xx_set_rate()
456 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; in samsung_pll45xx_set_rate()
457 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
463 con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) | in samsung_pll45xx_set_rate()
466 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) | in samsung_pll45xx_set_rate()
489 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
590 u32 con0, con1, lock; in samsung_pll46xx_set_rate() local
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| /drivers/pwm/ |
| D | pwm-mtk-disp.c | 32 unsigned int con0; member
111 mtk_disp_pwm_update_bits(mdp, mdp->data->con0, in mtk_disp_pwm_config()
226 mtk_disp_pwm_update_bits(mdp, mdp->data->con0, in mtk_disp_pwm_probe()
254 .con0 = 0xa8,
264 .con0 = 0x10,
274 .con0 = 0x18,
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| /drivers/video/fbdev/ |
| D | pxa168fb.h | 357 #define CFG_COS0(con0) (con0) argument
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| /drivers/video/fbdev/mmp/hw/ |
| D | mmp_ctrl.h | 585 #define CFG_COS0(con0) (con0) argument
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