| /drivers/gpu/drm/ |
| D | drm_client_modeset.c | 438 struct drm_crtc **crtcs, *crtc; in drm_client_pick_crtcs() local
453 crtcs = kcalloc(connector_count, sizeof(*crtcs), GFP_KERNEL); in drm_client_pick_crtcs()
454 if (!crtcs) in drm_client_pick_crtcs()
488 crtcs[n] = crtc; in drm_client_pick_crtcs()
489 memcpy(crtcs, best_crtcs, n * sizeof(*crtcs)); in drm_client_pick_crtcs()
491 crtcs, modes, n + 1, width, height); in drm_client_pick_crtcs()
494 memcpy(best_crtcs, crtcs, connector_count * sizeof(*crtcs)); in drm_client_pick_crtcs()
498 kfree(crtcs); in drm_client_pick_crtcs()
506 struct drm_crtc **crtcs, in drm_client_firmware_config() argument
590 if (crtcs[j] == new_crtc) { in drm_client_firmware_config()
[all …]
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| D | drm_atomic.c | 66 kfree(state->crtcs); in drm_atomic_state_default_release()
91 state->crtcs = kcalloc(dev->mode_config.num_crtc, in drm_atomic_state_init()
92 sizeof(*state->crtcs), GFP_KERNEL); in drm_atomic_state_init()
93 if (!state->crtcs) in drm_atomic_state_init()
171 struct drm_crtc *crtc = state->crtcs[i].ptr; in drm_atomic_state_default_clear()
177 state->crtcs[i].state); in drm_atomic_state_default_clear()
179 state->crtcs[i].ptr = NULL; in drm_atomic_state_default_clear()
180 state->crtcs[i].state = NULL; in drm_atomic_state_default_clear()
181 state->crtcs[i].old_state = NULL; in drm_atomic_state_default_clear()
182 state->crtcs[i].new_state = NULL; in drm_atomic_state_default_clear()
[all …]
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| D | drm_atomic_helper.c | 1455 old_state->crtcs[i].last_vblank_count = drm_crtc_vblank_count(crtc); in drm_atomic_helper_wait_for_vblanks()
1463 old_state->crtcs[i].last_vblank_count != in drm_atomic_helper_wait_for_vblanks()
1497 struct drm_crtc_commit *commit = old_state->crtcs[i].commit; in drm_atomic_helper_wait_for_flip_done()
1500 crtc = old_state->crtcs[i].ptr; in drm_atomic_helper_wait_for_flip_done()
2067 state->crtcs[i].commit = commit; in drm_atomic_helper_setup_commit()
2771 state->crtcs[i].state = old_crtc_state; in drm_atomic_helper_swap_state()
3247 state->crtcs[i].old_state = crtc->state; in drm_atomic_helper_commit_duplicated_state()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | dce_virtual.c | 236 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_virtual_crtc_init()
413 memset(adev->mode_info.crtcs, 0, sizeof(adev->mode_info.crtcs[0]) * AMDGPU_MAX_CRTCS); in dce_virtual_sw_fini()
469 if (adev->mode_info.crtcs[i]) in dce_virtual_hw_fini()
647 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_virtual_pageflip()
706 if (crtc >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[crtc]) { in dce_virtual_set_crtc_vblank_interrupt_state()
711 if (state && !adev->mode_info.crtcs[crtc]->vsync_timer_enabled) { in dce_virtual_set_crtc_vblank_interrupt_state()
713 hrtimer_init(&adev->mode_info.crtcs[crtc]->vblank_timer, in dce_virtual_set_crtc_vblank_interrupt_state()
715 hrtimer_set_expires(&adev->mode_info.crtcs[crtc]->vblank_timer, in dce_virtual_set_crtc_vblank_interrupt_state()
717 adev->mode_info.crtcs[crtc]->vblank_timer.function = in dce_virtual_set_crtc_vblank_interrupt_state()
719 hrtimer_start(&adev->mode_info.crtcs[crtc]->vblank_timer, in dce_virtual_set_crtc_vblank_interrupt_state()
[all …]
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| D | dce_v6_0.c | 193 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v6_0_page_flip()
1066 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v6_0_bandwidth_update()
1070 mode0 = &adev->mode_info.crtcs[i]->base.mode; in dce_v6_0_bandwidth_update()
1071 mode1 = &adev->mode_info.crtcs[i+1]->base.mode; in dce_v6_0_bandwidth_update()
1072 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); in dce_v6_0_bandwidth_update()
1073 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); in dce_v6_0_bandwidth_update()
1074 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); in dce_v6_0_bandwidth_update()
1075 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); in dce_v6_0_bandwidth_update()
2450 if (adev->mode_info.crtcs[i] && in dce_v6_0_crtc_disable()
2451 adev->mode_info.crtcs[i]->enabled && in dce_v6_0_crtc_disable()
[all …]
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| D | dce_v8_0.c | 186 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v8_0_page_flip()
1098 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v8_0_bandwidth_update()
1102 mode = &adev->mode_info.crtcs[i]->base.mode; in dce_v8_0_bandwidth_update()
1103 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v8_0_bandwidth_update()
1104 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i], in dce_v8_0_bandwidth_update()
2463 if (adev->mode_info.crtcs[i] && in dce_v8_0_crtc_disable()
2464 adev->mode_info.crtcs[i]->enabled && in dce_v8_0_crtc_disable()
2466 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v8_0_crtc_disable()
2593 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v8_0_crtc_init()
3090 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v8_0_pageflip_irq()
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| /drivers/gpu/drm/rcar-du/ |
| D | rcar_du_group.c | 108 rcrtc = rcdu->crtcs; in rcar_du_group_setup_didsr()
115 rcrtc = &rcdu->crtcs[rgrp->index * 2]; in rcar_du_group_setup_didsr()
216 struct rcar_du_crtc *rcrtc = &rgrp->dev->crtcs[rgrp->index * 2]; in __rcar_du_group_start_stop()
277 crtc = &rcdu->crtcs[index * 2]; in rcar_du_set_dpad0_vsp1_routing()
321 rcrtc = &rcdu->crtcs[rgrp->index * 2 + i]; in rcar_du_group_set_dpad_levels()
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| D | rcar_du_vsp.h | 60 unsigned int crtcs);
72 unsigned int crtcs) in rcar_du_vsp_init() argument
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| D | rcar_du_vsp.c | 345 unsigned int crtcs) in rcar_du_vsp_init() argument
349 unsigned int num_crtcs = hweight32(crtcs); in rcar_du_vsp_init()
384 ret = drm_universal_plane_init(rcdu->ddev, &plane->plane, crtcs, in rcar_du_vsp_init()
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| D | rcar_du_drv.h | 82 struct rcar_du_crtc crtcs[RCAR_DU_MAX_CRTCS]; member
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| D | rcar_du_kms.c | 589 rcdu->crtcs[i].vsp = &rcdu->vsps[j]; in rcar_du_vsps_init()
590 rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0; in rcar_du_vsps_init()
751 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[i]; in rcar_du_modeset_init()
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| D | rcar_du_plane.c | 756 unsigned int crtcs; in rcar_du_planes_init() local
766 crtcs = ((1 << rcdu->num_crtcs) - 1) & (3 << (2 * rgrp->index)); in rcar_du_planes_init()
776 ret = drm_universal_plane_init(rcdu->ddev, &plane->plane, crtcs, in rcar_du_planes_init()
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| /drivers/gpu/drm/sun4i/ |
| D | sun8i_dw_hdmi.c | 72 u32 crtcs = 0; in sun8i_dw_hdmi_find_possible_crtcs() local
86 crtcs |= drm_of_crtc_port_mask(drm, remote_port); in sun8i_dw_hdmi_find_possible_crtcs()
91 crtcs = drm_of_find_possible_crtcs(drm, node); in sun8i_dw_hdmi_find_possible_crtcs()
97 return crtcs; in sun8i_dw_hdmi_find_possible_crtcs()
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| /drivers/gpu/drm/radeon/ |
| D | rs690.c | 253 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); in rs690_line_buffer_adjust()
256 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); in rs690_line_buffer_adjust()
599 if (rdev->mode_info.crtcs[0]->base.enabled) in rs690_bandwidth_update()
600 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rs690_bandwidth_update()
601 if (rdev->mode_info.crtcs[1]->base.enabled) in rs690_bandwidth_update()
602 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rs690_bandwidth_update()
626 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); in rs690_bandwidth_update()
627 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); in rs690_bandwidth_update()
629 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true); in rs690_bandwidth_update()
630 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true); in rs690_bandwidth_update()
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| D | rv515.c | 1245 if (rdev->mode_info.crtcs[0]->base.enabled) in rv515_bandwidth_avivo_update()
1246 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rv515_bandwidth_avivo_update()
1247 if (rdev->mode_info.crtcs[1]->base.enabled) in rv515_bandwidth_avivo_update()
1248 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rv515_bandwidth_avivo_update()
1251 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); in rv515_bandwidth_avivo_update()
1252 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); in rv515_bandwidth_avivo_update()
1254 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false); in rv515_bandwidth_avivo_update()
1255 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false); in rv515_bandwidth_avivo_update()
1287 if (rdev->mode_info.crtcs[0]->base.enabled) in rv515_bandwidth_update()
1288 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rv515_bandwidth_update()
[all …]
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| D | rs600.c | 120 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip()
151 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip_pending()
905 if (rdev->mode_info.crtcs[0]->base.enabled) in rs600_bandwidth_update()
906 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rs600_bandwidth_update()
907 if (rdev->mode_info.crtcs[1]->base.enabled) in rs600_bandwidth_update()
908 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rs600_bandwidth_update()
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| D | radeon_display.c | 284 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in radeon_crtc_handle_vblank()
340 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && in radeon_crtc_handle_vblank()
365 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in radeon_crtc_handle_flip()
412 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; in radeon_flip_work_func()
686 rdev->mode_info.crtcs[index] = radeon_crtc; in radeon_crtc_init()
1949 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; in radeon_get_crtc_scanoutpos()
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| D | radeon_kms.c | 255 crtc = (struct drm_crtc *)minfo->crtcs[i]; in radeon_info_ioctl()
767 if (rdev->mode_info.crtcs[pipe]) { in radeon_get_vblank_counter_kms()
780 &rdev->mode_info.crtcs[pipe]->base.hwmode); in radeon_get_vblank_counter_kms()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_display.h | 391 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
392 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
408 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
409 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
410 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
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| /drivers/gpu/drm/vc4/ |
| D | vc4_kms.c | 156 if (!state->crtcs[i].ptr || !state->crtcs[i].commit) in vc4_atomic_complete_commit()
159 vc4_crtc = to_vc4_crtc(state->crtcs[i].ptr); in vc4_atomic_complete_commit()
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| /drivers/gpu/drm/arm/display/komeda/ |
| D | komeda_plane.c | 214 crtc = &kms->crtcs[i]; in get_possible_crtcs()
232 kcrtc = &kms->crtcs[i]; in komeda_set_crtc_plane_mask()
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| D | komeda_kms.h | 125 struct komeda_crtc crtcs[KOMEDA_MAX_PIPELINES]; member
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| D | komeda_wb_connector.c | 186 err = komeda_wb_connector_add(kms, &kms->crtcs[i]); in komeda_kms_add_wb_connectors()
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| /drivers/gpu/drm/msm/disp/mdp4/ |
| D | mdp4_irq.c | 85 if (status & mdp4_crtc_vblank(priv->crtcs[id])) in mdp4_irq()
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| /drivers/gpu/drm/msm/disp/mdp5/ |
| D | mdp5_irq.c | 98 if (status & mdp5_crtc_vblank(priv->crtcs[id])) in mdp5_irq()
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