1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * rcar_du_kms.c -- R-Car Display Unit Mode Setting
4 *
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
6 *
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 */
9
10 #include <drm/drm_atomic.h>
11 #include <drm/drm_atomic_helper.h>
12 #include <drm/drm_crtc.h>
13 #include <drm/drm_device.h>
14 #include <drm/drm_fb_cma_helper.h>
15 #include <drm/drm_gem_cma_helper.h>
16 #include <drm/drm_gem_framebuffer_helper.h>
17 #include <drm/drm_probe_helper.h>
18 #include <drm/drm_vblank.h>
19
20 #include <linux/of_graph.h>
21 #include <linux/wait.h>
22
23 #include "rcar_du_crtc.h"
24 #include "rcar_du_drv.h"
25 #include "rcar_du_encoder.h"
26 #include "rcar_du_kms.h"
27 #include "rcar_du_regs.h"
28 #include "rcar_du_vsp.h"
29 #include "rcar_du_writeback.h"
30
31 /* -----------------------------------------------------------------------------
32 * Format helpers
33 */
34
35 static const struct rcar_du_format_info rcar_du_format_infos[] = {
36 {
37 .fourcc = DRM_FORMAT_RGB565,
38 .v4l2 = V4L2_PIX_FMT_RGB565,
39 .bpp = 16,
40 .planes = 1,
41 .pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
42 .edf = PnDDCR4_EDF_NONE,
43 }, {
44 .fourcc = DRM_FORMAT_ARGB1555,
45 .v4l2 = V4L2_PIX_FMT_ARGB555,
46 .bpp = 16,
47 .planes = 1,
48 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
49 .edf = PnDDCR4_EDF_NONE,
50 }, {
51 .fourcc = DRM_FORMAT_XRGB1555,
52 .v4l2 = V4L2_PIX_FMT_XRGB555,
53 .bpp = 16,
54 .planes = 1,
55 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
56 .edf = PnDDCR4_EDF_NONE,
57 }, {
58 .fourcc = DRM_FORMAT_XRGB8888,
59 .v4l2 = V4L2_PIX_FMT_XBGR32,
60 .bpp = 32,
61 .planes = 1,
62 .pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
63 .edf = PnDDCR4_EDF_RGB888,
64 }, {
65 .fourcc = DRM_FORMAT_ARGB8888,
66 .v4l2 = V4L2_PIX_FMT_ABGR32,
67 .bpp = 32,
68 .planes = 1,
69 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_16BPP,
70 .edf = PnDDCR4_EDF_ARGB8888,
71 }, {
72 .fourcc = DRM_FORMAT_UYVY,
73 .v4l2 = V4L2_PIX_FMT_UYVY,
74 .bpp = 16,
75 .planes = 1,
76 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
77 .edf = PnDDCR4_EDF_NONE,
78 }, {
79 .fourcc = DRM_FORMAT_YUYV,
80 .v4l2 = V4L2_PIX_FMT_YUYV,
81 .bpp = 16,
82 .planes = 1,
83 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
84 .edf = PnDDCR4_EDF_NONE,
85 }, {
86 .fourcc = DRM_FORMAT_NV12,
87 .v4l2 = V4L2_PIX_FMT_NV12M,
88 .bpp = 12,
89 .planes = 2,
90 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
91 .edf = PnDDCR4_EDF_NONE,
92 }, {
93 .fourcc = DRM_FORMAT_NV21,
94 .v4l2 = V4L2_PIX_FMT_NV21M,
95 .bpp = 12,
96 .planes = 2,
97 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
98 .edf = PnDDCR4_EDF_NONE,
99 }, {
100 .fourcc = DRM_FORMAT_NV16,
101 .v4l2 = V4L2_PIX_FMT_NV16M,
102 .bpp = 16,
103 .planes = 2,
104 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
105 .edf = PnDDCR4_EDF_NONE,
106 },
107 /*
108 * The following formats are not supported on Gen2 and thus have no
109 * associated .pnmr or .edf settings.
110 */
111 {
112 .fourcc = DRM_FORMAT_RGB332,
113 .v4l2 = V4L2_PIX_FMT_RGB332,
114 .bpp = 8,
115 .planes = 1,
116 }, {
117 .fourcc = DRM_FORMAT_ARGB4444,
118 .v4l2 = V4L2_PIX_FMT_ARGB444,
119 .bpp = 16,
120 .planes = 1,
121 }, {
122 .fourcc = DRM_FORMAT_XRGB4444,
123 .v4l2 = V4L2_PIX_FMT_XRGB444,
124 .bpp = 16,
125 .planes = 1,
126 }, {
127 .fourcc = DRM_FORMAT_RGBA4444,
128 .v4l2 = V4L2_PIX_FMT_RGBA444,
129 .bpp = 16,
130 .planes = 1,
131 }, {
132 .fourcc = DRM_FORMAT_RGBX4444,
133 .v4l2 = V4L2_PIX_FMT_RGBX444,
134 .bpp = 16,
135 .planes = 1,
136 }, {
137 .fourcc = DRM_FORMAT_ABGR4444,
138 .v4l2 = V4L2_PIX_FMT_ABGR444,
139 .bpp = 16,
140 .planes = 1,
141 }, {
142 .fourcc = DRM_FORMAT_XBGR4444,
143 .v4l2 = V4L2_PIX_FMT_XBGR444,
144 .bpp = 16,
145 .planes = 1,
146 }, {
147 .fourcc = DRM_FORMAT_BGRA4444,
148 .v4l2 = V4L2_PIX_FMT_BGRA444,
149 .bpp = 16,
150 .planes = 1,
151 }, {
152 .fourcc = DRM_FORMAT_BGRX4444,
153 .v4l2 = V4L2_PIX_FMT_BGRX444,
154 .bpp = 16,
155 .planes = 1,
156 }, {
157 .fourcc = DRM_FORMAT_RGBA5551,
158 .v4l2 = V4L2_PIX_FMT_RGBA555,
159 .bpp = 16,
160 .planes = 1,
161 }, {
162 .fourcc = DRM_FORMAT_RGBX5551,
163 .v4l2 = V4L2_PIX_FMT_RGBX555,
164 .bpp = 16,
165 .planes = 1,
166 }, {
167 .fourcc = DRM_FORMAT_ABGR1555,
168 .v4l2 = V4L2_PIX_FMT_ABGR555,
169 .bpp = 16,
170 .planes = 1,
171 }, {
172 .fourcc = DRM_FORMAT_XBGR1555,
173 .v4l2 = V4L2_PIX_FMT_XBGR555,
174 .bpp = 16,
175 .planes = 1,
176 }, {
177 .fourcc = DRM_FORMAT_BGRA5551,
178 .v4l2 = V4L2_PIX_FMT_BGRA555,
179 .bpp = 16,
180 .planes = 1,
181 }, {
182 .fourcc = DRM_FORMAT_BGRX5551,
183 .v4l2 = V4L2_PIX_FMT_BGRX555,
184 .bpp = 16,
185 .planes = 1,
186 }, {
187 .fourcc = DRM_FORMAT_BGR888,
188 .v4l2 = V4L2_PIX_FMT_RGB24,
189 .bpp = 24,
190 .planes = 1,
191 }, {
192 .fourcc = DRM_FORMAT_RGB888,
193 .v4l2 = V4L2_PIX_FMT_BGR24,
194 .bpp = 24,
195 .planes = 1,
196 }, {
197 .fourcc = DRM_FORMAT_RGBA8888,
198 .v4l2 = V4L2_PIX_FMT_BGRA32,
199 .bpp = 32,
200 .planes = 1,
201 }, {
202 .fourcc = DRM_FORMAT_RGBX8888,
203 .v4l2 = V4L2_PIX_FMT_BGRX32,
204 .bpp = 32,
205 .planes = 1,
206 }, {
207 .fourcc = DRM_FORMAT_ABGR8888,
208 .v4l2 = V4L2_PIX_FMT_RGBA32,
209 .bpp = 32,
210 .planes = 1,
211 }, {
212 .fourcc = DRM_FORMAT_XBGR8888,
213 .v4l2 = V4L2_PIX_FMT_RGBX32,
214 .bpp = 32,
215 .planes = 1,
216 }, {
217 .fourcc = DRM_FORMAT_BGRA8888,
218 .v4l2 = V4L2_PIX_FMT_ARGB32,
219 .bpp = 32,
220 .planes = 1,
221 }, {
222 .fourcc = DRM_FORMAT_BGRX8888,
223 .v4l2 = V4L2_PIX_FMT_XRGB32,
224 .bpp = 32,
225 .planes = 1,
226 }, {
227 .fourcc = DRM_FORMAT_YVYU,
228 .v4l2 = V4L2_PIX_FMT_YVYU,
229 .bpp = 16,
230 .planes = 1,
231 }, {
232 .fourcc = DRM_FORMAT_NV61,
233 .v4l2 = V4L2_PIX_FMT_NV61M,
234 .bpp = 16,
235 .planes = 2,
236 }, {
237 .fourcc = DRM_FORMAT_YUV420,
238 .v4l2 = V4L2_PIX_FMT_YUV420M,
239 .bpp = 12,
240 .planes = 3,
241 }, {
242 .fourcc = DRM_FORMAT_YVU420,
243 .v4l2 = V4L2_PIX_FMT_YVU420M,
244 .bpp = 12,
245 .planes = 3,
246 }, {
247 .fourcc = DRM_FORMAT_YUV422,
248 .v4l2 = V4L2_PIX_FMT_YUV422M,
249 .bpp = 16,
250 .planes = 3,
251 }, {
252 .fourcc = DRM_FORMAT_YVU422,
253 .v4l2 = V4L2_PIX_FMT_YVU422M,
254 .bpp = 16,
255 .planes = 3,
256 }, {
257 .fourcc = DRM_FORMAT_YUV444,
258 .v4l2 = V4L2_PIX_FMT_YUV444M,
259 .bpp = 24,
260 .planes = 3,
261 }, {
262 .fourcc = DRM_FORMAT_YVU444,
263 .v4l2 = V4L2_PIX_FMT_YVU444M,
264 .bpp = 24,
265 .planes = 3,
266 },
267 };
268
rcar_du_format_info(u32 fourcc)269 const struct rcar_du_format_info *rcar_du_format_info(u32 fourcc)
270 {
271 unsigned int i;
272
273 for (i = 0; i < ARRAY_SIZE(rcar_du_format_infos); ++i) {
274 if (rcar_du_format_infos[i].fourcc == fourcc)
275 return &rcar_du_format_infos[i];
276 }
277
278 return NULL;
279 }
280
281 /* -----------------------------------------------------------------------------
282 * Frame buffer
283 */
284
rcar_du_dumb_create(struct drm_file * file,struct drm_device * dev,struct drm_mode_create_dumb * args)285 int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
286 struct drm_mode_create_dumb *args)
287 {
288 struct rcar_du_device *rcdu = dev->dev_private;
289 unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
290 unsigned int align;
291
292 /*
293 * The R8A7779 DU requires a 16 pixels pitch alignment as documented,
294 * but the R8A7790 DU seems to require a 128 bytes pitch alignment.
295 */
296 if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
297 align = 128;
298 else
299 align = 16 * args->bpp / 8;
300
301 args->pitch = roundup(min_pitch, align);
302
303 return drm_gem_cma_dumb_create_internal(file, dev, args);
304 }
305
306 static struct drm_framebuffer *
rcar_du_fb_create(struct drm_device * dev,struct drm_file * file_priv,const struct drm_mode_fb_cmd2 * mode_cmd)307 rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv,
308 const struct drm_mode_fb_cmd2 *mode_cmd)
309 {
310 struct rcar_du_device *rcdu = dev->dev_private;
311 const struct rcar_du_format_info *format;
312 unsigned int max_pitch;
313 unsigned int align;
314 unsigned int i;
315
316 format = rcar_du_format_info(mode_cmd->pixel_format);
317 if (format == NULL) {
318 dev_dbg(dev->dev, "unsupported pixel format %08x\n",
319 mode_cmd->pixel_format);
320 return ERR_PTR(-EINVAL);
321 }
322
323 if (rcdu->info->gen < 3) {
324 /*
325 * On Gen2 the DU limits the pitch to 4095 pixels and requires
326 * buffers to be aligned to a 16 pixels boundary (or 128 bytes
327 * on some platforms).
328 */
329 unsigned int bpp = format->planes == 1 ? format->bpp / 8 : 1;
330
331 max_pitch = 4095 * bpp;
332
333 if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
334 align = 128;
335 else
336 align = 16 * bpp;
337 } else {
338 /*
339 * On Gen3 the memory interface is handled by the VSP that
340 * limits the pitch to 65535 bytes and has no alignment
341 * constraint.
342 */
343 max_pitch = 65535;
344 align = 1;
345 }
346
347 if (mode_cmd->pitches[0] & (align - 1) ||
348 mode_cmd->pitches[0] > max_pitch) {
349 dev_dbg(dev->dev, "invalid pitch value %u\n",
350 mode_cmd->pitches[0]);
351 return ERR_PTR(-EINVAL);
352 }
353
354 for (i = 1; i < format->planes; ++i) {
355 if (mode_cmd->pitches[i] != mode_cmd->pitches[0]) {
356 dev_dbg(dev->dev,
357 "luma and chroma pitches do not match\n");
358 return ERR_PTR(-EINVAL);
359 }
360 }
361
362 return drm_gem_fb_create(dev, file_priv, mode_cmd);
363 }
364
365 /* -----------------------------------------------------------------------------
366 * Atomic Check and Update
367 */
368
rcar_du_atomic_check(struct drm_device * dev,struct drm_atomic_state * state)369 static int rcar_du_atomic_check(struct drm_device *dev,
370 struct drm_atomic_state *state)
371 {
372 struct rcar_du_device *rcdu = dev->dev_private;
373 int ret;
374
375 ret = drm_atomic_helper_check(dev, state);
376 if (ret)
377 return ret;
378
379 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
380 return 0;
381
382 return rcar_du_atomic_check_planes(dev, state);
383 }
384
rcar_du_atomic_commit_tail(struct drm_atomic_state * old_state)385 static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state)
386 {
387 struct drm_device *dev = old_state->dev;
388 struct rcar_du_device *rcdu = dev->dev_private;
389 struct drm_crtc_state *crtc_state;
390 struct drm_crtc *crtc;
391 unsigned int i;
392
393 /*
394 * Store RGB routing to DPAD0 and DPAD1, the hardware will be configured
395 * when starting the CRTCs.
396 */
397 rcdu->dpad1_source = -1;
398
399 for_each_new_crtc_in_state(old_state, crtc, crtc_state, i) {
400 struct rcar_du_crtc_state *rcrtc_state =
401 to_rcar_crtc_state(crtc_state);
402 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
403
404 if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD0))
405 rcdu->dpad0_source = rcrtc->index;
406
407 if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
408 rcdu->dpad1_source = rcrtc->index;
409 }
410
411 /* Apply the atomic update. */
412 drm_atomic_helper_commit_modeset_disables(dev, old_state);
413 drm_atomic_helper_commit_planes(dev, old_state,
414 DRM_PLANE_COMMIT_ACTIVE_ONLY);
415 drm_atomic_helper_commit_modeset_enables(dev, old_state);
416
417 drm_atomic_helper_commit_hw_done(old_state);
418 drm_atomic_helper_wait_for_flip_done(dev, old_state);
419
420 drm_atomic_helper_cleanup_planes(dev, old_state);
421 }
422
423 /* -----------------------------------------------------------------------------
424 * Initialization
425 */
426
427 static const struct drm_mode_config_helper_funcs rcar_du_mode_config_helper = {
428 .atomic_commit_tail = rcar_du_atomic_commit_tail,
429 };
430
431 static const struct drm_mode_config_funcs rcar_du_mode_config_funcs = {
432 .fb_create = rcar_du_fb_create,
433 .atomic_check = rcar_du_atomic_check,
434 .atomic_commit = drm_atomic_helper_commit,
435 };
436
rcar_du_encoders_init_one(struct rcar_du_device * rcdu,enum rcar_du_output output,struct of_endpoint * ep)437 static int rcar_du_encoders_init_one(struct rcar_du_device *rcdu,
438 enum rcar_du_output output,
439 struct of_endpoint *ep)
440 {
441 struct device_node *entity;
442 int ret;
443
444 /* Locate the connected entity and initialize the encoder. */
445 entity = of_graph_get_remote_port_parent(ep->local_node);
446 if (!entity) {
447 dev_dbg(rcdu->dev, "unconnected endpoint %pOF, skipping\n",
448 ep->local_node);
449 return -ENODEV;
450 }
451
452 if (!of_device_is_available(entity)) {
453 dev_dbg(rcdu->dev,
454 "connected entity %pOF is disabled, skipping\n",
455 entity);
456 of_node_put(entity);
457 return -ENODEV;
458 }
459
460 ret = rcar_du_encoder_init(rcdu, output, entity);
461 if (ret && ret != -EPROBE_DEFER && ret != -ENOLINK)
462 dev_warn(rcdu->dev,
463 "failed to initialize encoder %pOF on output %u (%d), skipping\n",
464 entity, output, ret);
465
466 of_node_put(entity);
467
468 return ret;
469 }
470
rcar_du_encoders_init(struct rcar_du_device * rcdu)471 static int rcar_du_encoders_init(struct rcar_du_device *rcdu)
472 {
473 struct device_node *np = rcdu->dev->of_node;
474 struct device_node *ep_node;
475 unsigned int num_encoders = 0;
476
477 /*
478 * Iterate over the endpoints and create one encoder for each output
479 * pipeline.
480 */
481 for_each_endpoint_of_node(np, ep_node) {
482 enum rcar_du_output output;
483 struct of_endpoint ep;
484 unsigned int i;
485 int ret;
486
487 ret = of_graph_parse_endpoint(ep_node, &ep);
488 if (ret < 0) {
489 of_node_put(ep_node);
490 return ret;
491 }
492
493 /* Find the output route corresponding to the port number. */
494 for (i = 0; i < RCAR_DU_OUTPUT_MAX; ++i) {
495 if (rcdu->info->routes[i].possible_crtcs &&
496 rcdu->info->routes[i].port == ep.port) {
497 output = i;
498 break;
499 }
500 }
501
502 if (i == RCAR_DU_OUTPUT_MAX) {
503 dev_warn(rcdu->dev,
504 "port %u references unexisting output, skipping\n",
505 ep.port);
506 continue;
507 }
508
509 /* Process the output pipeline. */
510 ret = rcar_du_encoders_init_one(rcdu, output, &ep);
511 if (ret < 0) {
512 if (ret == -EPROBE_DEFER) {
513 of_node_put(ep_node);
514 return ret;
515 }
516
517 continue;
518 }
519
520 num_encoders++;
521 }
522
523 return num_encoders;
524 }
525
rcar_du_properties_init(struct rcar_du_device * rcdu)526 static int rcar_du_properties_init(struct rcar_du_device *rcdu)
527 {
528 /*
529 * The color key is expressed as an RGB888 triplet stored in a 32-bit
530 * integer in XRGB8888 format. Bit 24 is used as a flag to disable (0)
531 * or enable source color keying (1).
532 */
533 rcdu->props.colorkey =
534 drm_property_create_range(rcdu->ddev, 0, "colorkey",
535 0, 0x01ffffff);
536 if (rcdu->props.colorkey == NULL)
537 return -ENOMEM;
538
539 return 0;
540 }
541
rcar_du_vsps_init(struct rcar_du_device * rcdu)542 static int rcar_du_vsps_init(struct rcar_du_device *rcdu)
543 {
544 const struct device_node *np = rcdu->dev->of_node;
545 struct of_phandle_args args;
546 struct {
547 struct device_node *np;
548 unsigned int crtcs_mask;
549 } vsps[RCAR_DU_MAX_VSPS] = { { NULL, }, };
550 unsigned int vsps_count = 0;
551 unsigned int cells;
552 unsigned int i;
553 int ret;
554
555 /*
556 * First parse the DT vsps property to populate the list of VSPs. Each
557 * entry contains a pointer to the VSP DT node and a bitmask of the
558 * connected DU CRTCs.
559 */
560 cells = of_property_count_u32_elems(np, "vsps") / rcdu->num_crtcs - 1;
561 if (cells > 1)
562 return -EINVAL;
563
564 for (i = 0; i < rcdu->num_crtcs; ++i) {
565 unsigned int j;
566
567 ret = of_parse_phandle_with_fixed_args(np, "vsps", cells, i,
568 &args);
569 if (ret < 0)
570 goto error;
571
572 /*
573 * Add the VSP to the list or update the corresponding existing
574 * entry if the VSP has already been added.
575 */
576 for (j = 0; j < vsps_count; ++j) {
577 if (vsps[j].np == args.np)
578 break;
579 }
580
581 if (j < vsps_count)
582 of_node_put(args.np);
583 else
584 vsps[vsps_count++].np = args.np;
585
586 vsps[j].crtcs_mask |= BIT(i);
587
588 /* Store the VSP pointer and pipe index in the CRTC. */
589 rcdu->crtcs[i].vsp = &rcdu->vsps[j];
590 rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0;
591 }
592
593 /*
594 * Then initialize all the VSPs from the node pointers and CRTCs bitmask
595 * computed previously.
596 */
597 for (i = 0; i < vsps_count; ++i) {
598 struct rcar_du_vsp *vsp = &rcdu->vsps[i];
599
600 vsp->index = i;
601 vsp->dev = rcdu;
602
603 ret = rcar_du_vsp_init(vsp, vsps[i].np, vsps[i].crtcs_mask);
604 if (ret < 0)
605 goto error;
606 }
607
608 return 0;
609
610 error:
611 for (i = 0; i < ARRAY_SIZE(vsps); ++i)
612 of_node_put(vsps[i].np);
613
614 return ret;
615 }
616
rcar_du_modeset_init(struct rcar_du_device * rcdu)617 int rcar_du_modeset_init(struct rcar_du_device *rcdu)
618 {
619 static const unsigned int mmio_offsets[] = {
620 DU0_REG_OFFSET, DU2_REG_OFFSET
621 };
622
623 struct drm_device *dev = rcdu->ddev;
624 struct drm_encoder *encoder;
625 unsigned int dpad0_sources;
626 unsigned int num_encoders;
627 unsigned int num_groups;
628 unsigned int swindex;
629 unsigned int hwindex;
630 unsigned int i;
631 int ret;
632
633 drm_mode_config_init(dev);
634
635 dev->mode_config.min_width = 0;
636 dev->mode_config.min_height = 0;
637 dev->mode_config.normalize_zpos = true;
638 dev->mode_config.funcs = &rcar_du_mode_config_funcs;
639 dev->mode_config.helper_private = &rcar_du_mode_config_helper;
640
641 if (rcdu->info->gen < 3) {
642 dev->mode_config.max_width = 4095;
643 dev->mode_config.max_height = 2047;
644 } else {
645 /*
646 * The Gen3 DU uses the VSP1 for memory access, and is limited
647 * to frame sizes of 8190x8190.
648 */
649 dev->mode_config.max_width = 8190;
650 dev->mode_config.max_height = 8190;
651 }
652
653 rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
654
655 ret = rcar_du_properties_init(rcdu);
656 if (ret < 0)
657 return ret;
658
659 /*
660 * Initialize vertical blanking interrupts handling. Start with vblank
661 * disabled for all CRTCs.
662 */
663 ret = drm_vblank_init(dev, rcdu->num_crtcs);
664 if (ret < 0)
665 return ret;
666
667 /* Initialize the groups. */
668 num_groups = DIV_ROUND_UP(rcdu->num_crtcs, 2);
669
670 for (i = 0; i < num_groups; ++i) {
671 struct rcar_du_group *rgrp = &rcdu->groups[i];
672
673 mutex_init(&rgrp->lock);
674
675 rgrp->dev = rcdu;
676 rgrp->mmio_offset = mmio_offsets[i];
677 rgrp->index = i;
678 /* Extract the channel mask for this group only. */
679 rgrp->channels_mask = (rcdu->info->channels_mask >> (2 * i))
680 & GENMASK(1, 0);
681 rgrp->num_crtcs = hweight8(rgrp->channels_mask);
682
683 /*
684 * If we have more than one CRTCs in this group pre-associate
685 * the low-order planes with CRTC 0 and the high-order planes
686 * with CRTC 1 to minimize flicker occurring when the
687 * association is changed.
688 */
689 rgrp->dptsr_planes = rgrp->num_crtcs > 1
690 ? (rcdu->info->gen >= 3 ? 0x04 : 0xf0)
691 : 0;
692
693 if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
694 ret = rcar_du_planes_init(rgrp);
695 if (ret < 0)
696 return ret;
697 }
698 }
699
700 /* Initialize the compositors. */
701 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
702 ret = rcar_du_vsps_init(rcdu);
703 if (ret < 0)
704 return ret;
705 }
706
707 /* Create the CRTCs. */
708 for (swindex = 0, hwindex = 0; swindex < rcdu->num_crtcs; ++hwindex) {
709 struct rcar_du_group *rgrp;
710
711 /* Skip unpopulated DU channels. */
712 if (!(rcdu->info->channels_mask & BIT(hwindex)))
713 continue;
714
715 rgrp = &rcdu->groups[hwindex / 2];
716
717 ret = rcar_du_crtc_create(rgrp, swindex++, hwindex);
718 if (ret < 0)
719 return ret;
720 }
721
722 /* Initialize the encoders. */
723 ret = rcar_du_encoders_init(rcdu);
724 if (ret < 0)
725 return ret;
726
727 if (ret == 0) {
728 dev_err(rcdu->dev, "error: no encoder could be initialized\n");
729 return -EINVAL;
730 }
731
732 num_encoders = ret;
733
734 /*
735 * Set the possible CRTCs and possible clones. There's always at least
736 * one way for all encoders to clone each other, set all bits in the
737 * possible clones field.
738 */
739 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
740 struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
741 const struct rcar_du_output_routing *route =
742 &rcdu->info->routes[renc->output];
743
744 encoder->possible_crtcs = route->possible_crtcs;
745 encoder->possible_clones = (1 << num_encoders) - 1;
746 }
747
748 /* Create the writeback connectors. */
749 if (rcdu->info->gen >= 3) {
750 for (i = 0; i < rcdu->num_crtcs; ++i) {
751 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[i];
752
753 ret = rcar_du_writeback_init(rcdu, rcrtc);
754 if (ret < 0)
755 return ret;
756 }
757 }
758
759 /*
760 * Initialize the default DPAD0 source to the index of the first DU
761 * channel that can be connected to DPAD0. The exact value doesn't
762 * matter as it should be overwritten by mode setting for the RGB
763 * output, but it is nonetheless required to ensure a valid initial
764 * hardware configuration on Gen3 where DU0 can't always be connected to
765 * DPAD0.
766 */
767 dpad0_sources = rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs;
768 rcdu->dpad0_source = ffs(dpad0_sources) - 1;
769
770 drm_mode_config_reset(dev);
771
772 drm_kms_helper_poll_init(dev);
773
774 return 0;
775 }
776