Home
last modified time | relevance | path

Searched refs:ctrl0 (Results 1 – 25 of 25) sorted by relevance

/drivers/net/ethernet/neterion/vxge/
Dvxge-config.h1113 #define VXGE_HW_NODBW_GET_TYPE(ctrl0) vxge_bVALn(ctrl0, 0, 8) argument
1117 #define VXGE_HW_NODBW_GET_LAST_TXD_NUMBER(ctrl0) vxge_bVALn(ctrl0, 32, 8) argument
1120 #define VXGE_HW_NODBW_GET_NO_SNOOP(ctrl0) vxge_bVALn(ctrl0, 56, 8) argument
1263 #define VXGE_HW_FIFO_TXD_T_CODE_GET(ctrl0) vxge_bVALn(ctrl0, 12, 4) argument
1388 #define VXGE_HW_RING_RXD_RTH_BUCKET_GET(ctrl0) vxge_bVALn(ctrl0, 0, 7) argument
1392 #define VXGE_HW_RING_RXD_FAST_PATH_ELIGIBLE_GET(ctrl0) vxge_bVALn(ctrl0, 8, 1) argument
1394 #define VXGE_HW_RING_RXD_L3_CKSUM_CORRECT_GET(ctrl0) vxge_bVALn(ctrl0, 9, 1) argument
1396 #define VXGE_HW_RING_RXD_L4_CKSUM_CORRECT_GET(ctrl0) vxge_bVALn(ctrl0, 10, 1) argument
1398 #define VXGE_HW_RING_RXD_T_CODE_GET(ctrl0) vxge_bVALn(ctrl0, 12, 4) argument
1403 #define VXGE_HW_RING_RXD_SYN_GET(ctrl0) vxge_bVALn(ctrl0, 16, 1) argument
[all …]
/drivers/crypto/bcm/
Dspu2.c308 static void spu2_dump_fmd_ctrl0(u64 ctrl0) in spu2_dump_fmd_ctrl0() argument
321 packet_log(" FMD CTRL0 %#16llx\n", ctrl0); in spu2_dump_fmd_ctrl0()
322 if (ctrl0 & SPU2_CIPH_ENCRYPT_EN) in spu2_dump_fmd_ctrl0()
327 ciph_type = (ctrl0 & SPU2_CIPH_TYPE) >> SPU2_CIPH_TYPE_SHIFT; in spu2_dump_fmd_ctrl0()
332 ciph_mode = (ctrl0 & SPU2_CIPH_MODE) >> SPU2_CIPH_MODE_SHIFT; in spu2_dump_fmd_ctrl0()
337 cfb = (ctrl0 & SPU2_CFB_MASK) >> SPU2_CFB_MASK_SHIFT; in spu2_dump_fmd_ctrl0()
340 proto = (ctrl0 & SPU2_PROTO_SEL) >> SPU2_PROTO_SEL_SHIFT; in spu2_dump_fmd_ctrl0()
343 if (ctrl0 & SPU2_HASH_FIRST) in spu2_dump_fmd_ctrl0()
348 if (ctrl0 & SPU2_CHK_TAG) in spu2_dump_fmd_ctrl0()
351 hash_type = (ctrl0 & SPU2_HASH_TYPE) >> SPU2_HASH_TYPE_SHIFT; in spu2_dump_fmd_ctrl0()
[all …]
Dspu2.h76 u64 ctrl0; member
/drivers/phy/samsung/
Dphy-exynos5250-usb2.c200 u32 ctrl0; in exynos5250_power_on() local
244 ctrl0 = readl(drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); in exynos5250_power_on()
246 ctrl0 &= ~EXYNOS_5250_HOSTPHYCTRL0_FSEL_MASK; in exynos5250_power_on()
247 ctrl0 |= drv->ref_reg_val << in exynos5250_power_on()
251 ctrl0 &= ~(EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST | in exynos5250_power_on()
256 ctrl0 |= EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST | in exynos5250_power_on()
259 writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); in exynos5250_power_on()
261 ctrl0 &= ~(EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST | in exynos5250_power_on()
263 writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); in exynos5250_power_on()
326 u32 ctrl0; in exynos5250_power_off() local
[all …]
/drivers/input/rmi4/
Drmi_f01.c115 u8 ctrl0; member
411 &f01->device_control.ctrl0); in rmi_f01_probe()
421 f01->device_control.ctrl0 &= ~RMI_F01_CTRL0_NOSLEEP_BIT; in rmi_f01_probe()
424 f01->device_control.ctrl0 |= RMI_F01_CTRL0_NOSLEEP_BIT; in rmi_f01_probe()
433 if ((f01->device_control.ctrl0 & RMI_F01_CTRL0_SLEEP_MODE_MASK) != in rmi_f01_probe()
437 f01->device_control.ctrl0 &= ~RMI_F01_CTRL0_SLEEP_MODE_MASK; in rmi_f01_probe()
440 f01->device_control.ctrl0 |= RMI_F01_CTRL0_CONFIGURED_BIT; in rmi_f01_probe()
443 f01->device_control.ctrl0); in rmi_f01_probe()
589 f01->device_control.ctrl0); in rmi_f01_config()
636 f01->device_control.ctrl0 & RMI_F01_CTRL0_NOSLEEP_BIT; in rmi_f01_suspend()
[all …]
/drivers/media/platform/vsp1/
Dvsp1_sru.c40 u32 ctrl0; member
55 .ctrl0 = VI6_SRU_CTRL0_PARAMS(256, 4) | VI6_SRU_CTRL0_EN,
58 .ctrl0 = VI6_SRU_CTRL0_PARAMS(256, 4) | VI6_SRU_CTRL0_EN,
61 .ctrl0 = VI6_SRU_CTRL0_PARAMS(384, 5) | VI6_SRU_CTRL0_EN,
64 .ctrl0 = VI6_SRU_CTRL0_PARAMS(384, 5) | VI6_SRU_CTRL0_EN,
67 .ctrl0 = VI6_SRU_CTRL0_PARAMS(511, 6) | VI6_SRU_CTRL0_EN,
70 .ctrl0 = VI6_SRU_CTRL0_PARAMS(511, 6) | VI6_SRU_CTRL0_EN,
279 u32 ctrl0; in sru_configure_stream() local
287 ctrl0 = VI6_SRU_CTRL0_PARAM2 | VI6_SRU_CTRL0_PARAM3 in sru_configure_stream()
290 ctrl0 = VI6_SRU_CTRL0_PARAM3; in sru_configure_stream()
[all …]
/drivers/pinctrl/intel/
Dpinctrl-cherryview.c724 u32 ctrl0, ctrl1; in chv_pin_dbg_show() local
729 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); in chv_pin_dbg_show()
735 if (ctrl0 & CHV_PADCTRL0_GPIOEN) { in chv_pin_dbg_show()
740 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK; in chv_pin_dbg_show()
746 seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1); in chv_pin_dbg_show()
942 u32 ctrl0; in chv_gpio_set_direction() local
946 ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK; in chv_gpio_set_direction()
948 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; in chv_gpio_set_direction()
950 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; in chv_gpio_set_direction()
951 chv_writel(ctrl0, reg); in chv_gpio_set_direction()
[all …]
/drivers/mmc/host/
Dmxs-mmc.c88 u32 ctrl0, ctrl1; in mxs_mmc_reset() local
95 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC; in mxs_mmc_reset()
112 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; in mxs_mmc_reset()
116 writel(ctrl0, ssp->base + HW_SSP_CTRL0); in mxs_mmc_reset()
254 u32 ctrl0, cmd0, cmd1; in mxs_mmc_bc() local
256 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC; in mxs_mmc_bc()
261 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; in mxs_mmc_bc()
265 ssp->ssp_pio_words[0] = ctrl0; in mxs_mmc_bc()
289 u32 ctrl0, cmd0, cmd1; in mxs_mmc_ac() local
298 ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp; in mxs_mmc_ac()
[all …]
/drivers/staging/ralink-gdma/
Dralink-gdma.c275 u32 ctrl0, ctrl1; in rt305x_gdma_start_transfer() local
278 ctrl0 = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id)); in rt305x_gdma_start_transfer()
279 if (unlikely(ctrl0 & GDMA_REG_CTRL0_ENABLE)) { in rt305x_gdma_start_transfer()
281 chan->id, ctrl0); in rt305x_gdma_start_transfer()
290 ctrl0 = GDMA_REG_CTRL0_DST_ADDR_FIXED | in rt305x_gdma_start_transfer()
296 ctrl0 = GDMA_REG_CTRL0_SRC_ADDR_FIXED | in rt305x_gdma_start_transfer()
306 ctrl0 = GDMA_REG_CTRL0_SW_MODE | in rt305x_gdma_start_transfer()
315 ctrl0 |= (sg->len << GDMA_REG_CTRL0_TX_SHIFT) | in rt305x_gdma_start_transfer()
327 gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), ctrl0); in rt305x_gdma_start_transfer()
352 u32 ctrl0, ctrl1; in rt3883_gdma_start_transfer() local
[all …]
/drivers/net/can/cc770/
Dcc770.c143 cc770_write_reg(priv, msgobj[mo].ctrl0, in enable_all_objs()
162 cc770_write_reg(priv, msgobj[mo].ctrl0, in enable_all_objs()
183 cc770_write_reg(priv, msgobj[mo].ctrl0, in disable_all_objs()
191 cc770_write_reg(priv, msgobj[mo].ctrl0, in disable_all_objs()
263 cc770_write_reg(priv, msgobj[mo].ctrl0, in chipset_init()
266 cc770_write_reg(priv, msgobj[mo].ctrl0, in chipset_init()
397 cc770_write_reg(priv, msgobj[mo].ctrl0, in cc770_tx()
422 cc770_write_reg(priv, msgobj[mo].ctrl0, in cc770_tx()
613 if (!(cc770_read_reg(priv, msgobj[mo].ctrl0) & in cc770_rx_interrupt()
631 cc770_write_reg(priv, msgobj[mo].ctrl0, in cc770_rx_interrupt()
[all …]
Dcc770.h14 u8 ctrl0; member
/drivers/spi/
Dspi-mxs.c175 u32 ctrl0; in mxs_spi_txrx_dma() local
192 ctrl0 = readl(ssp->base + HW_SSP_CTRL0); in mxs_spi_txrx_dma()
193 ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC | in mxs_spi_txrx_dma()
195 ctrl0 |= BM_SSP_CTRL0_DATA_XFER; in mxs_spi_txrx_dma()
198 ctrl0 |= BM_SSP_CTRL0_READ; in mxs_spi_txrx_dma()
210 ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC; in mxs_spi_txrx_dma()
213 ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT; in mxs_spi_txrx_dma()
214 ctrl0 |= min; in mxs_spi_txrx_dma()
217 dma_xfer[sg_count].pio[0] = ctrl0; in mxs_spi_txrx_dma()
/drivers/thermal/
Darmada_thermal.c325 u32 ctrl0; in armada_select_channel() local
334 regmap_read(priv->syscon, data->syscon_control0_off, &ctrl0); in armada_select_channel()
335 ctrl0 &= ~CONTROL0_TSEN_START; in armada_select_channel()
336 regmap_write(priv->syscon, data->syscon_control0_off, ctrl0); in armada_select_channel()
339 ctrl0 &= ~(CONTROL0_TSEN_MODE_MASK << CONTROL0_TSEN_MODE_SHIFT); in armada_select_channel()
344 ctrl0 |= CONTROL0_TSEN_MODE_EXTERNAL << in armada_select_channel()
347 ctrl0 &= ~(CONTROL0_TSEN_CHAN_MASK << CONTROL0_TSEN_CHAN_SHIFT); in armada_select_channel()
348 ctrl0 |= (channel - 1) << CONTROL0_TSEN_CHAN_SHIFT; in armada_select_channel()
352 regmap_write(priv->syscon, data->syscon_control0_off, ctrl0); in armada_select_channel()
356 ctrl0 |= CONTROL0_TSEN_START; in armada_select_channel()
[all …]
/drivers/power/supply/
Dtps65090-charger.c64 uint8_t ctrl0 = 0; in tps65090_enable_charging() local
70 &ctrl0); in tps65090_enable_charging()
78 (ctrl0 | TPS65090_CHARGER_ENABLE)); in tps65090_enable_charging()
/drivers/net/ethernet/huawei/hinic/
Dhinic_hw_eqs.c421 u32 addr, val, ctrl0; in set_ctrl0() local
434 ctrl0 = HINIC_AEQ_CTRL_0_SET(msix_entry->entry, INT_IDX) | in set_ctrl0()
440 val |= ctrl0; in set_ctrl0()
455 ctrl0 = HINIC_CEQ_CTRL_0_SET(msix_entry->entry, INTR_IDX) | in set_ctrl0()
462 val |= ctrl0; in set_ctrl0()
/drivers/crypto/chelsio/
Dchcr_ipsec.c437 u32 ctrl0, qidx; in copy_cpltx_pktxt() local
453 ctrl0 = TXPKT_OPCODE_V(CPL_TX_PKT_XT) | TXPKT_INTF_V(pi->tx_chan) | in copy_cpltx_pktxt()
460 cpl->ctrl0 = htonl(ctrl0); in copy_cpltx_pktxt()
/drivers/net/ethernet/intel/ixgb/
Dixgb_main.c228 u32 ctrl0 = IXGB_READ_REG(hw, CTRL0); in ixgb_up() local
230 if (!(ctrl0 & IXGB_CTRL0_JFE)) { in ixgb_up()
231 ctrl0 |= IXGB_CTRL0_JFE; in ixgb_up()
232 IXGB_WRITE_REG(hw, CTRL0, ctrl0); in ixgb_up()
292 u32 ctrl0 = IXGB_READ_REG(hw, CTRL0); in ixgb_reset() local
293 if (!(ctrl0 & IXGB_CTRL0_JFE)) { in ixgb_reset()
294 ctrl0 |= IXGB_CTRL0_JFE; in ixgb_reset()
295 IXGB_WRITE_REG(hw, CTRL0, ctrl0); in ixgb_reset()
/drivers/net/ethernet/marvell/mvpp2/
Dmvpp2_main.c4909 u32 old_ctrl0, ctrl0; in mvpp2_xlg_config() local
4912 old_ctrl0 = ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_xlg_config()
4915 ctrl0 |= MVPP22_XLG_CTRL0_MAC_RESET_DIS; in mvpp2_xlg_config()
4918 ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; in mvpp2_xlg_config()
4920 ctrl0 &= ~MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; in mvpp2_xlg_config()
4923 ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; in mvpp2_xlg_config()
4925 ctrl0 &= ~MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; in mvpp2_xlg_config()
4931 if (old_ctrl0 != ctrl0) in mvpp2_xlg_config()
4932 writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_xlg_config()
4947 u32 old_ctrl0, ctrl0; in mvpp2_gmac_config() local
[all …]
/drivers/net/wireless/ath/ath9k/
Dar9003_paprd.c141 static const u32 ctrl0[3] = { in ar9003_paprd_setup_single_table() local
184 REG_RMW_FIELD(ah, ctrl0[i], in ar9003_paprd_setup_single_table()
198 REG_RMW_FIELD(ah, ctrl0[i], in ar9003_paprd_setup_single_table()
/drivers/net/ethernet/chelsio/cxgb4/
Dsge.c1359 u32 wr_mid, ctrl0, op; in cxgb4_eth_xmit() local
1588 ctrl0 = TXPKT_OPCODE_V(CPL_TX_PKT_XT) | TXPKT_INTF_V(pi->tx_chan) | in cxgb4_eth_xmit()
1591 ctrl0 |= TXPKT_TSTAMP_F; in cxgb4_eth_xmit()
1594 ctrl0 |= TXPKT_OVLAN_IDX_V(q->dcb_prio); in cxgb4_eth_xmit()
1596 ctrl0 |= TXPKT_T5_OVLAN_IDX_V(q->dcb_prio); in cxgb4_eth_xmit()
1598 cpl->ctrl0 = htonl(ctrl0); in cxgb4_eth_xmit()
1899 cpl->ctrl0 = cpu_to_be32(TXPKT_OPCODE_V(CPL_TX_PKT_XT) | in cxgb4_vf_eth_xmit()
Dt4_msg.h819 __be32 ctrl0; member
/drivers/video/fbdev/mmp/hw/
Dmmp_ctrl.h1025 u32 ctrl0; member
1057 u32 ctrl0; member
/drivers/gpu/drm/msm/adreno/
Da6xx_gpu_state.c204 static int vbif_debugbus_read(struct msm_gpu *gpu, u32 ctrl0, u32 ctrl1, in vbif_debugbus_read() argument
209 gpu_write(gpu, ctrl0, reg); in vbif_debugbus_read()
/drivers/net/wireless/ath/ath6kl/
Dhtc_mbox.c360 int ctrl0, int ctrl1) in ath6kl_htc_tx_prep_pkt() argument
371 hdr->ctrl[0] = ctrl0; in ath6kl_htc_tx_prep_pkt()
/drivers/net/ethernet/chelsio/cxgb4vf/
Dsge.c1357 cpl->ctrl0 = cpu_to_be32(TXPKT_OPCODE_V(CPL_TX_PKT_XT) | in t4vf_eth_xmit()