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Searched refs:ctrlreg (Results 1 – 10 of 10) sorted by relevance

/drivers/pinctrl/sirf/
Dpinctrl-atlas6.c146 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
173 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
201 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
229 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
253 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
301 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
335 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
355 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
372 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
389 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
[all …]
Dpinctrl-prima2.c150 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
177 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
205 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
233 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
254 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
299 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
333 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
350 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
381 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
398 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
[all …]
Dpinctrl-sirf.h63 unsigned long ctrlreg; member
Dpinctrl-sirf.c171 readl(spmx->rsc_virtbase + mux->ctrlreg); in sirfsoc_pinmux_endisable()
174 writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg); in sirfsoc_pinmux_endisable()
/drivers/rtc/
Drtc-rx8010.c66 u8 ctrlreg; member
154 rx8010->ctrlreg = ctrl | RX8010_CTRL_STOP; in rx8010_set_time()
156 rx8010->ctrlreg); in rx8010_set_time()
177 rx8010->ctrlreg = ctrl & ~RX8010_CTRL_STOP; in rx8010_set_time()
179 rx8010->ctrlreg); in rx8010_set_time()
244 rx8010->ctrlreg = (ctrl[1] & ~RX8010_CTRL_TEST); in rx8010_init_client()
272 t->enabled = !!(rx8010->ctrlreg & RX8010_CTRL_AIE); in rx8010_read_alarm()
291 if (rx8010->ctrlreg & (RX8010_CTRL_AIE | RX8010_CTRL_UIE)) { in rx8010_set_alarm()
292 rx8010->ctrlreg &= ~(RX8010_CTRL_AIE | RX8010_CTRL_UIE); in rx8010_set_alarm()
294 rx8010->ctrlreg); in rx8010_set_alarm()
[all …]
/drivers/video/fbdev/
Dgxt4500.c380 u32 ctrlreg, tmp; in gxt4500_set_par() local
394 ctrlreg = readreg(par, DTG_CONTROL); in gxt4500_set_par()
395 ctrlreg &= ~(DTG_CTL_ENABLE | DTG_CTL_SCREEN_REFRESH); in gxt4500_set_par()
396 writereg(par, DTG_CONTROL, ctrlreg); in gxt4500_set_par()
449 ctrlreg |= DTG_CTL_ENABLE | DTG_CTL_SCREEN_REFRESH; in gxt4500_set_par()
450 writereg(par, DTG_CONTROL, ctrlreg); in gxt4500_set_par()
494 ctrlreg = readreg(par, SYNC_CTL) & in gxt4500_set_par()
498 ctrlreg |= SYNC_CTL_SYNC_ON_RGB; in gxt4500_set_par()
500 ctrlreg |= SYNC_CTL_HSYNC_INV; in gxt4500_set_par()
502 ctrlreg |= SYNC_CTL_VSYNC_INV; in gxt4500_set_par()
[all …]
/drivers/isdn/hardware/mISDN/
Davmfritz.c123 u8 ctrlreg; member
324 fc->ctrlreg |= AVM_STATUS0_ENA_IRQ; in enable_hwirq()
325 outb(fc->ctrlreg, fc->addr + 2); in enable_hwirq()
331 fc->ctrlreg &= ~AVM_STATUS0_ENA_IRQ; in disable_hwirq()
332 outb(fc->ctrlreg, fc->addr + 2); in disable_hwirq()
671 outb(fc->ctrlreg | AVM_STATUS0_RES_TIMER, fc->addr + 2); in avm_fritzv2_interrupt()
673 outb(fc->ctrlreg, fc->addr + 2); in avm_fritzv2_interrupt()
747 fc->ctrlreg = AVM_STATUS0_RESET | AVM_STATUS0_DIS_TIMER; in reset_avm()
750 fc->ctrlreg = AVM_STATUS0_RESET; in reset_avm()
759 fc->ctrlreg = AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER; in reset_avm()
[all …]
Dnetjet.c79 u8 ctrlreg; member
281 card->ctrlreg = 0x40; /* Reset Off and status read clear */ in nj_reset()
283 card->ctrlreg = 0x00; /* Reset Off and status read clear */ in nj_reset()
284 outb(card->ctrlreg, card->base + NJ_CTRL); in nj_reset()
/drivers/bus/
Dmvebu-mbus.c208 u32 ctrlreg = readl(addr + WIN_CTRL_OFF); in mvebu_mbus_read_window() local
210 if (!(ctrlreg & WIN_CTRL_ENABLE)) { in mvebu_mbus_read_window()
218 *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1; in mvebu_mbus_read_window()
221 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT; in mvebu_mbus_read_window()
224 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT; in mvebu_mbus_read_window()
/drivers/phy/st/
Dphy-miphy28lp.c1164 u32 ctrlreg; in miphy28lp_of_probe() local
1184 if (!of_property_read_u32_index(np, "st,syscfg", i, &ctrlreg)) in miphy28lp_of_probe()
1185 miphy_phy->syscfg_reg[i] = ctrlreg; in miphy28lp_of_probe()