| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_dccg.c | 32 #define TO_DCN_DCCG(dccg)\ argument
33 container_of(dccg, struct dcn_dccg, base)
45 dccg->ctx->logger
47 void dccg2_update_dpp_dto(struct dccg *dccg, in dccg2_update_dpp_dto() argument
52 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_update_dpp_dto()
54 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
55 int ref_dppclk = dccg->ref_dppclk; in dccg2_update_dpp_dto()
98 void dccg2_get_dccg_ref_freq(struct dccg *dccg, in dccg2_get_dccg_ref_freq() argument
102 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_get_dccg_ref_freq()
120 void dccg2_init(struct dccg *dccg) in dccg2_init() argument
[all …]
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| D | dcn20_dccg.h | 94 struct dccg base;
100 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk, bool raise_divider_only);
102 void dccg2_get_dccg_ref_freq(struct dccg *dccg,
106 void dccg2_init(struct dccg *dccg);
108 struct dccg *dccg2_create(
114 void dcn_dccg_destroy(struct dccg **dccg);
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| D | dcn20_hwseq.c | 2005 if (res_pool->dccg->funcs->dccg_init) in dcn20_fpga_init_hw()
2006 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn20_fpga_init_hw()
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| D | dcn20_resource.c | 1296 if (pool->base.dccg != NULL) in destruct()
1297 dcn_dccg_destroy(&pool->base.dccg); in destruct()
3418 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in construct()
3419 if (pool->base.dccg == NULL) { in construct()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | dccg.h | 31 struct dccg { struct
39 void (*update_dpp_dto)(struct dccg *dccg, argument
43 void (*get_dccg_ref_freq)(struct dccg *dccg,
46 void (*dccg_init)(struct dccg *dccg);
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| D | clk_mgr.h | 196 struct dccg;
198 …clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg);
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| D | clk_mgr_internal.h | 198 struct dccg *dccg; member
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 115 clk_mgr->dccg->funcs->update_dpp_dto( in dcn20_update_clocks_update_dpp_dto()
116 clk_mgr->dccg, dpp_inst, dppclk_khz, false); in dcn20_update_clocks_update_dpp_dto()
175 clk_mgr->dccg->ref_dppclk = khz; in request_voltage_and_program_global_dpp_clk()
290 clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, true); in dcn2_update_clocks()
307 clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, false); in dcn2_update_clocks()
372 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz; in dcn2_update_clocks_fpga()
431 struct dccg *dccg) in dcn20_clk_mgr_construct() argument
440 clk_mgr->dccg = dccg; in dcn20_clk_mgr_construct()
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| D | dcn20_clk_mgr.h | 29 void dcn2_update_clocks(struct clk_mgr *dccg,
44 struct dccg *dccg);
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| D | clk_mgr.c | 69 … clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg) in dc_clk_mgr_create() argument
116 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
134 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.h | 37 struct dccg *dccg);
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| D | rn_clk_mgr.c | 514 struct dccg *dccg) in rn_clk_mgr_construct() argument
525 clk_mgr->dccg = dccg; in rn_clk_mgr_construct()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
| D | dce_clk_mgr.h | 48 int dce12_get_dp_ref_freq_khz(struct clk_mgr *dccg);
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 222 struct dccg *dccg; member
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer.c | 1188 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init) in dcn10_init_hw()
1189 dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn10_init_hw()
1221 if (res_pool->dccg && res_pool->hubbub) { in dcn10_init_hw()
1223 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn10_init_hw()
2303 if (dc->res_pool->dccg) in update_dchubp_dpp()
2304 dc->res_pool->dccg->funcs->update_dpp_dto( in update_dchubp_dpp()
2305 dc->res_pool->dccg, in update_dchubp_dpp()
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 938 if (pool->base.dccg != NULL) in destruct()
939 dcn_dccg_destroy(&pool->base.dccg); in destruct()
1512 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in construct()
1513 if (pool->base.dccg == NULL) { in construct()
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_hw_sequencer.c | 2439 struct clk_mgr *dccg = dc->clk_mgr; in dce110_prepare_bandwidth() local
2443 dccg->funcs->update_clocks( in dce110_prepare_bandwidth()
2444 dccg, in dce110_prepare_bandwidth()
2453 struct clk_mgr *dccg = dc->clk_mgr; in dce110_optimize_bandwidth() local
2457 dccg->funcs->update_clocks( in dce110_optimize_bandwidth()
2458 dccg, in dce110_optimize_bandwidth()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc.c | 692 dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); in construct()
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