Home
last modified time | relevance | path

Searched refs:divider_reg (Results 1 – 4 of 4) sorted by relevance

/drivers/clk/
Dclk-xgene.c430 void __iomem *divider_reg; /* CSR for divider */ member
539 if (pclk->param.divider_reg) { in xgene_clk_recalc_rate()
540 data = xgene_clk_read(pclk->param.divider_reg + in xgene_clk_recalc_rate()
569 if (pclk->param.divider_reg) { in xgene_clk_set_rate()
578 data = xgene_clk_read(pclk->param.divider_reg + in xgene_clk_set_rate()
583 xgene_clk_write(data, pclk->param.divider_reg + in xgene_clk_set_rate()
604 if (pclk->param.divider_reg) { in xgene_clk_round_rate()
681 parameters.divider_reg = NULL; in xgene_devclk_init()
698 parameters.divider_reg = map_res; in xgene_devclk_init()
736 if (parameters.divider_reg) in xgene_devclk_init()
[all …]
/drivers/clk/mvebu/
Dap-cpu-clk.c40 unsigned int divider_reg; member
78 .divider_reg = AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET,
112 .divider_reg = AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET,
151 cpu_clkdiv_reg = clk->pll_regs->divider_reg + in ap_cpu_clk_recalc_rate()
167 cpu_clkdiv_reg = clk->pll_regs->divider_reg + in ap_cpu_clk_set_rate()
/drivers/clk/mediatek/
Dclk-mtk.h66 uint32_t divider_reg; member
136 .divider_reg = _div_reg, \
Dclk-mtk.c207 div->reg = base + mc->divider_reg; in mtk_clk_register_composite()