Searched refs:grph (Results 1 – 11 of 11) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hubbub.c | 282 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub2_get_dcc_compression_cap()
283 output->grph.rgb.max_compressed_blk_size = 256; in hubbub2_get_dcc_compression_cap()
284 output->grph.rgb.independent_64b_blks = false; in hubbub2_get_dcc_compression_cap()
287 output->grph.rgb.max_uncompressed_blk_size = 128; in hubbub2_get_dcc_compression_cap()
288 output->grph.rgb.max_compressed_blk_size = 128; in hubbub2_get_dcc_compression_cap()
289 output->grph.rgb.independent_64b_blks = false; in hubbub2_get_dcc_compression_cap()
292 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub2_get_dcc_compression_cap()
293 output->grph.rgb.max_compressed_blk_size = 64; in hubbub2_get_dcc_compression_cap()
294 output->grph.rgb.independent_64b_blks = true; in hubbub2_get_dcc_compression_cap()
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| D | dcn20_hubp.c | 718 if (address->grph.addr.quad_part == 0) in hubp2_program_surface_flip_and_addr()
725 if (address->grph.meta_addr.quad_part != 0) { in hubp2_program_surface_flip_and_addr()
728 address->grph.meta_addr.high_part); in hubp2_program_surface_flip_and_addr()
732 address->grph.meta_addr.low_part); in hubp2_program_surface_flip_and_addr()
737 address->grph.addr.high_part); in hubp2_program_surface_flip_and_addr()
741 address->grph.addr.low_part); in hubp2_program_surface_flip_and_addr()
895 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); in hubp2_is_flip_pending()
898 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); in hubp2_is_flip_pending()
903 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) in hubp2_is_flip_pending()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hubbub.c | 919 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub1_get_dcc_compression_cap()
920 output->grph.rgb.max_compressed_blk_size = 256; in hubbub1_get_dcc_compression_cap()
921 output->grph.rgb.independent_64b_blks = false; in hubbub1_get_dcc_compression_cap()
924 output->grph.rgb.max_uncompressed_blk_size = 128; in hubbub1_get_dcc_compression_cap()
925 output->grph.rgb.max_compressed_blk_size = 128; in hubbub1_get_dcc_compression_cap()
926 output->grph.rgb.independent_64b_blks = false; in hubbub1_get_dcc_compression_cap()
929 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub1_get_dcc_compression_cap()
930 output->grph.rgb.max_compressed_blk_size = 64; in hubbub1_get_dcc_compression_cap()
931 output->grph.rgb.independent_64b_blks = true; in hubbub1_get_dcc_compression_cap()
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| D | dcn10_hubp.c | 378 if (address->grph.addr.quad_part == 0) in hubp1_program_surface_flip_and_addr()
385 if (address->grph.meta_addr.quad_part != 0) { in hubp1_program_surface_flip_and_addr()
388 address->grph.meta_addr.high_part); in hubp1_program_surface_flip_and_addr()
392 address->grph.meta_addr.low_part); in hubp1_program_surface_flip_and_addr()
397 address->grph.addr.high_part); in hubp1_program_surface_flip_and_addr()
401 address->grph.addr.low_part); in hubp1_program_surface_flip_and_addr()
731 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); in hubp1_is_flip_pending()
734 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); in hubp1_is_flip_pending()
739 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) in hubp1_is_flip_pending()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_debug.c | 84 plane_state->address.grph.addr.quad_part, in pre_surface_trace()
85 plane_state->address.grph.meta_addr.quad_part, in pre_surface_trace()
196 update->flip_addr->address.grph.addr.quad_part, in update_surface_trace()
197 update->flip_addr->address.grph.meta_addr.quad_part, in update_surface_trace()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc_hw_types.h | 75 } grph; member
132 } grph; member
156 } grph; member
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| D | dc.h | 145 } grph; member
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_mem_input.c | 705 if (address->grph.addr.quad_part == 0) in dce_mi_program_surface_flip_and_addr()
707 program_pri_addr(dce_mi, address->grph.addr); in dce_mi_program_surface_flip_and_addr()
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm.c | 2738 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0) in fill_plane_dcc_attributes()
2747 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); in fill_plane_dcc_attributes()
2748 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); in fill_plane_dcc_attributes()
2781 address->grph.addr.low_part = lower_32_bits(afb->address); in fill_plane_buffer_attributes()
2782 address->grph.addr.high_part = upper_32_bits(afb->address); in fill_plane_buffer_attributes()
5804 bundle->flip_addrs[planes_count].address.grph.addr.high_part, in amdgpu_dm_commit_planes()
5805 bundle->flip_addrs[planes_count].address.grph.addr.low_part); in amdgpu_dm_commit_planes()
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_mem_input_v.c | 137 addr->grph.addr); in program_addr()
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| D | dce110_hw_sequencer.c | 2546 pipe_ctx->plane_state->address.grph.addr.high_part, in dce110_program_front_end_for_pipe()
2547 pipe_ctx->plane_state->address.grph.addr.low_part, in dce110_program_front_end_for_pipe()
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