| /drivers/gpu/drm/panel/ |
| D | panel-simple.c | 167 m->hdisplay, m->vdisplay, m->vrefresh); in panel_simple_get_display_modes()
517 .hdisplay = 480,
542 .hdisplay = 800,
593 .hdisplay = 1024,
638 .hdisplay = 1366,
662 .hdisplay = 1366,
685 .hdisplay = 1366,
708 .hdisplay = 1920,
764 .hdisplay = 1280,
788 .hdisplay = 800,
[all …]
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| D | panel-arm-versatile.c | 138 .hdisplay = 320,
162 .hdisplay = 640,
185 .hdisplay = 176,
209 .hdisplay = 240,
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| D | panel-tpo-tpg110.c | 111 .hdisplay = 800,
128 .hdisplay = 640,
145 .hdisplay = 480,
162 .hdisplay = 480,
179 .hdisplay = 400,
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| D | panel-sharp-lq101r1sx01.c | 137 err = mipi_dsi_dcs_set_column_address(left, 0, mode->hdisplay / 2 - 1); in sharp_setup_symmetrical_split()
149 err = mipi_dsi_dcs_set_column_address(right, mode->hdisplay / 2, in sharp_setup_symmetrical_split()
150 mode->hdisplay - 1); in sharp_setup_symmetrical_split()
270 .hdisplay = 2560,
288 default_mode.hdisplay, default_mode.vdisplay, in sharp_panel_get_modes()
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| /drivers/gpu/drm/tve200/ |
| D | tve200_display.c | 81 if (!(mode->hdisplay == 352 && mode->vdisplay == 240) && /* SIF(525) */ in tve200_display_check()
82 !(mode->hdisplay == 352 && mode->vdisplay == 288) && /* CIF(625) */ in tve200_display_check()
83 !(mode->hdisplay == 640 && mode->vdisplay == 480) && /* VGA */ in tve200_display_check()
84 !(mode->hdisplay == 720 && mode->vdisplay == 480) && /* D1 */ in tve200_display_check()
85 !(mode->hdisplay == 720 && mode->vdisplay == 576)) { /* D1 */ in tve200_display_check()
87 mode->hdisplay, mode->vdisplay); in tve200_display_check()
104 if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0]) { in tve200_display_check()
154 if ((mode->hdisplay == 352 && mode->vdisplay == 240) || /* SIF(525) */ in tve200_display_enable()
155 (mode->hdisplay == 352 && mode->vdisplay == 288)) { /* CIF(625) */ in tve200_display_enable()
158 } else if (mode->hdisplay == 640 && mode->vdisplay == 480) { in tve200_display_enable()
[all …]
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| /drivers/gpu/drm/ |
| D | drm_modes.c | 140 struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay, in drm_cvt_mode() argument
161 if (!hdisplay || !vdisplay) in drm_cvt_mode()
182 hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); in drm_cvt_mode()
191 drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; in drm_cvt_mode()
213 if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay)) in drm_cvt_mode()
215 else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay)) in drm_cvt_mode()
217 else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay)) in drm_cvt_mode()
219 else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay)) in drm_cvt_mode()
221 else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay)) in drm_cvt_mode()
273 hblank = drm_mode->hdisplay * hblank_percentage / in drm_cvt_mode()
[all …]
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| /drivers/gpu/drm/hisilicon/kirin/kirin960/ |
| D | dw_drm_dsi.c | 88 mode->hdisplay, mode->vdisplay, in dsi_encoder_phy_mode_valid()
90 if ((mode->hdisplay == 1920 && mode->vdisplay == 1080 && mode->clock == 148500) || in dsi_encoder_phy_mode_valid()
91 (mode->hdisplay == 1920 && mode->vdisplay == 1080 && mode->clock == 80192) || in dsi_encoder_phy_mode_valid()
92 (mode->hdisplay == 1920 && mode->vdisplay == 1080 && mode->clock == 74250) || in dsi_encoder_phy_mode_valid()
93 (mode->hdisplay == 1920 && mode->vdisplay == 1080 && mode->clock == 61855) || in dsi_encoder_phy_mode_valid()
94 (mode->hdisplay == 1680 && mode->vdisplay == 1050 && mode->clock == 147116) || in dsi_encoder_phy_mode_valid()
95 (mode->hdisplay == 1680 && mode->vdisplay == 1050 && mode->clock == 146250) || in dsi_encoder_phy_mode_valid()
96 (mode->hdisplay == 1680 && mode->vdisplay == 1050 && mode->clock == 144589) || in dsi_encoder_phy_mode_valid()
97 (mode->hdisplay == 1600 && mode->vdisplay == 1200 && mode->clock == 160961) || in dsi_encoder_phy_mode_valid()
98 (mode->hdisplay == 1600 && mode->vdisplay == 900 && mode->clock == 118963) || in dsi_encoder_phy_mode_valid()
[all …]
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_encoders.c | 153 unsigned hblank = native_mode->htotal - native_mode->hdisplay; in amdgpu_panel_mode_fixup()
155 unsigned hover = native_mode->hsync_start - native_mode->hdisplay; in amdgpu_panel_mode_fixup()
163 adjusted_mode->hdisplay = native_mode->hdisplay; in amdgpu_panel_mode_fixup()
166 adjusted_mode->htotal = native_mode->hdisplay + hblank; in amdgpu_panel_mode_fixup()
167 adjusted_mode->hsync_start = native_mode->hdisplay + hover; in amdgpu_panel_mode_fixup()
176 adjusted_mode->crtc_hdisplay = native_mode->hdisplay; in amdgpu_panel_mode_fixup()
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| D | amdgpu_connectors.c | 388 if (native_mode->hdisplay != 0 && in amdgpu_connector_lcd_native_mode()
396 } else if (native_mode->hdisplay != 0 && in amdgpu_connector_lcd_native_mode()
405 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); in amdgpu_connector_lcd_native_mode()
450 if (common_modes[i].w > native_mode->hdisplay || in amdgpu_connector_add_common_modes()
452 (common_modes[i].w == native_mode->hdisplay && in amdgpu_connector_add_common_modes()
620 if (mode->hdisplay != native_mode->hdisplay || in amdgpu_connector_fixup_lcd_native_mode()
629 if (mode->hdisplay == native_mode->hdisplay && in amdgpu_connector_fixup_lcd_native_mode()
687 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) in amdgpu_connector_lvds_mode_valid()
697 if ((mode->hdisplay > native_mode->hdisplay) || in amdgpu_connector_lvds_mode_valid()
703 if ((mode->hdisplay != native_mode->hdisplay) || in amdgpu_connector_lvds_mode_valid()
[all …]
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | tvnv17.c | 207 for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) { in nv17_tv_get_ld_modes()
219 if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay && in nv17_tv_get_ld_modes()
237 int hdisplay; in nv17_tv_get_hd_modes() member
253 if (modes[i].hdisplay > output_mode->hdisplay || in nv17_tv_get_hd_modes()
257 if (modes[i].hdisplay == output_mode->hdisplay && in nv17_tv_get_hd_modes()
263 mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay, in nv17_tv_get_hd_modes()
270 if (output_mode->hdisplay <= 720 in nv17_tv_get_hd_modes()
271 || output_mode->hdisplay >= 1920) { in nv17_tv_get_hd_modes()
273 mode->hsync_start = (mode->hdisplay + (mode->htotal in nv17_tv_get_hd_modes()
274 - mode->hdisplay) * 9 / 10) & ~7; in nv17_tv_get_hd_modes()
[all …]
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| D | dfp.c | 191 mode->hdisplay > nv_connector->native_mode->hdisplay || in nv04_dfp_mode_fixup()
300 regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1; in nv04_dfp_mode_set()
303 (output_mode->hsync_start - output_mode->hdisplay) >= in nv04_dfp_mode_set()
305 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay; in nv04_dfp_mode_set()
311 regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1; in nv04_dfp_mode_set()
334 else if (adjusted_mode->hdisplay == output_mode->hdisplay && in nv04_dfp_mode_set()
374 mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay; in nv04_dfp_mode_set()
375 panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay; in nv04_dfp_mode_set()
393 diff = output_mode->hdisplay - in nv04_dfp_mode_set()
404 scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay; in nv04_dfp_mode_set()
[all …]
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| D | tvmodesnv17.c | 325 uint64_t rs[] = {mode->hdisplay * id3, in tv_setup_filter()
328 do_div(rs[0], overscan * tv_norm->tv_enc_mode.hdisplay); in tv_setup_filter()
559 hmargin = (output_mode->hdisplay - crtc_mode->hdisplay) / 2; in nv17_ctv_update_rescaler()
562 hmargin = interpolate(0, min(hmargin, output_mode->hdisplay/20), in nv17_ctv_update_rescaler()
567 hratio = crtc_mode->hdisplay * 0x800 / in nv17_ctv_update_rescaler()
568 (output_mode->hdisplay - 2*hmargin); in nv17_ctv_update_rescaler()
573 regs->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - hmargin - 1; in nv17_ctv_update_rescaler()
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| /drivers/gpu/drm/gma500/ |
| D | mdfld_tmd_vid.c | 47 mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo; in tmd_vid_get_config_mode()
49 mode->hsync_start = mode->hdisplay + \ in tmd_vid_get_config_mode()
55 mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \ in tmd_vid_get_config_mode()
67 dev_dbg(dev->dev, "hdisplay is %d\n", mode->hdisplay); in tmd_vid_get_config_mode()
77 mode->hdisplay = 480; in tmd_vid_get_config_mode()
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| D | oaktrail_lvds.c | 132 (mode->hdisplay != adjusted_mode->crtc_hdisplay)) { in oaktrail_lvds_mode_set()
134 (mode->hdisplay * adjusted_mode->crtc_vdisplay)) in oaktrail_lvds_mode_set()
137 mode->vdisplay) > (mode->hdisplay * in oaktrail_lvds_mode_set()
226 mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo; in oaktrail_lvds_get_configuration_mode()
228 mode->hsync_start = mode->hdisplay + \ in oaktrail_lvds_get_configuration_mode()
234 mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \ in oaktrail_lvds_get_configuration_mode()
246 pr_info("hdisplay is %d\n", mode->hdisplay); in oaktrail_lvds_get_configuration_mode()
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| D | cdv_intel_lvds.c | 251 if (mode->hdisplay > fixed_mode->hdisplay) in cdv_intel_lvds_mode_valid()
286 adjusted_mode->hdisplay = panel_fixed_mode->hdisplay; in cdv_intel_lvds_mode_fixup()
359 if (mode->hdisplay != adjusted_mode->hdisplay || in cdv_intel_lvds_mode_set()
455 if (crtc->saved_mode.hdisplay != 0 && in cdv_intel_lvds_set_property()
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| /drivers/gpu/drm/radeon/ |
| D | radeon_encoders.c | 329 unsigned hblank = native_mode->htotal - native_mode->hdisplay; in radeon_panel_mode_fixup()
331 unsigned hover = native_mode->hsync_start - native_mode->hdisplay; in radeon_panel_mode_fixup()
340 adjusted_mode->hdisplay = native_mode->hdisplay; in radeon_panel_mode_fixup()
344 adjusted_mode->htotal = native_mode->hdisplay + hblank; in radeon_panel_mode_fixup()
345 adjusted_mode->hsync_start = native_mode->hdisplay + hover; in radeon_panel_mode_fixup()
355 adjusted_mode->crtc_hdisplay = native_mode->hdisplay; in radeon_panel_mode_fixup()
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| /drivers/gpu/drm/i915/display/ |
| D | dvo_ns2501.c | 532 mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal); in ns2501_mode_valid()
540 if ((mode->hdisplay == 640 && mode->vdisplay == 480 && mode->clock == 25175) || in ns2501_mode_valid()
541 (mode->hdisplay == 800 && mode->vdisplay == 600 && mode->clock == 40000) || in ns2501_mode_valid()
542 (mode->hdisplay == 1024 && mode->vdisplay == 768 && mode->clock == 65000)) { in ns2501_mode_valid()
559 mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal); in ns2501_mode_set()
591 if (mode->hdisplay == 640 && mode->vdisplay == 480) in ns2501_mode_set()
593 else if (mode->hdisplay == 800 && mode->vdisplay == 600) in ns2501_mode_set()
595 else if (mode->hdisplay == 1024 && mode->vdisplay == 768) in ns2501_mode_set()
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| D | intel_tv.c | 998 mode->hdisplay = in intel_tv_mode_to_mode()
1000 mode->hsync_start = mode->hdisplay + in intel_tv_mode_to_mode()
1044 mode->hdisplay, mode->vdisplay, in intel_tv_mode_to_mode()
1050 int hdisplay, int left_margin, in intel_tv_scale_mode_horiz() argument
1053 int hsync_start = mode->hsync_start - mode->hdisplay + right_margin; in intel_tv_scale_mode_horiz()
1054 int hsync_end = mode->hsync_end - mode->hdisplay + right_margin; in intel_tv_scale_mode_horiz()
1055 int new_htotal = mode->htotal * hdisplay / in intel_tv_scale_mode_horiz()
1056 (mode->hdisplay - left_margin - right_margin); in intel_tv_scale_mode_horiz()
1060 mode->hdisplay = hdisplay; in intel_tv_scale_mode_horiz()
1061 mode->hsync_start = hdisplay + hsync_start * new_htotal / mode->htotal; in intel_tv_scale_mode_horiz()
[all …]
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| D | dvo_ch7017.c | 302 horizontal_active_pixel_input = mode->hdisplay & 0x00ff; in ch7017_mode_set()
305 horizontal_active_pixel_output = mode->hdisplay & 0x00ff; in ch7017_mode_set()
307 active_input_line_output = ((mode->hdisplay & 0x0700) >> 8) | in ch7017_mode_set()
311 (mode->hdisplay & 0x0700) >> 8; in ch7017_mode_set()
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| /drivers/gpu/drm/pl111/ |
| D | pl111_display.c | 64 bw = bw * mode->hdisplay * mode->vdisplay * cpp; in pl111_mode_valid()
73 mode->hdisplay, mode->vdisplay, in pl111_mode_valid()
79 mode->hdisplay, mode->vdisplay, in pl111_mode_valid()
93 if (mode->hdisplay % 16) in pl111_display_check()
106 if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0]) in pl111_display_check()
147 ppl = (mode->hdisplay / 16) - 1; in pl111_display_enable()
149 hfp = mode->hsync_start - mode->hdisplay - 1; in pl111_display_enable()
157 cpl = mode->hdisplay - 1; in pl111_display_enable()
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| /drivers/gpu/drm/tilcdc/ |
| D | tilcdc_plane.c | 48 if (crtc_state->mode.hdisplay != state->crtc_w || in tilcdc_plane_atomic_check()
52 crtc_state->mode.hdisplay, crtc_state->mode.vdisplay, in tilcdc_plane_atomic_check()
57 pitch = crtc_state->mode.hdisplay * in tilcdc_plane_atomic_check()
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| D | tilcdc_crtc.c | 317 hfp = mode->hsync_start - mode->hdisplay; in tilcdc_crtc_set_mode()
324 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw); in tilcdc_crtc_set_mode()
344 reg = (((mode->hdisplay >> 4) - 1) << 4) | in tilcdc_crtc_set_mode()
349 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3; in tilcdc_crtc_set_mode()
741 if (mode->hdisplay > tilcdc_crtc_max_width(crtc)) in tilcdc_crtc_mode_valid()
745 if (mode->hdisplay & 0xf) in tilcdc_crtc_mode_valid()
752 mode->hdisplay, mode->vdisplay, in tilcdc_crtc_mode_valid()
756 hfp = mode->hsync_start - mode->hdisplay; in tilcdc_crtc_mode_valid()
805 if (mode->hdisplay > priv->max_width) in tilcdc_crtc_mode_valid()
809 bandwidth = mode->hdisplay * mode->vdisplay * in tilcdc_crtc_mode_valid()
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| /drivers/gpu/drm/hisilicon/kirin/ |
| D | kirin_drm_dpe.c | 81 u32 hdisplay; member
408 writel((DPE_HEIGHT(mode->vdisplay) << 16) | DPE_WIDTH(mode->hdisplay), in dpe_dpp_init()
410 writel((DPE_HEIGHT(mode->vdisplay) << 16) | DPE_WIDTH(mode->hdisplay), in dpe_dpp_init()
505 hfp = mode->hsync_start - mode->hdisplay; in dpe_dbuf_init()
514 if (mode->hdisplay * mode->vdisplay >= RES_4K_PHONE) in dpe_dbuf_init()
521 thd_cg_out = (DFS_TIME * adj_mode->clock * 1000UL * mode->hdisplay) / in dpe_dbuf_init()
522 (((hsw + hbp + hfp) + mode->hdisplay) * 6 * 1000000UL); in dpe_dbuf_init()
533 sram_min_support_depth = dfs_time_min * mode->hdisplay / in dpe_dbuf_init()
542 writel(mode->hdisplay * mode->vdisplay, dbuf_base + DBUF_FRM_SIZE); in dpe_dbuf_init()
543 writel(DPE_WIDTH(mode->hdisplay), dbuf_base + DBUF_FRM_HSIZE); in dpe_dbuf_init()
[all …]
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| /drivers/gpu/drm/exynos/ |
| D | exynos_hdmi.c | 922 mode->hdisplay, mode->vdisplay, mode->vrefresh, in hdmi_mode_valid()
1018 m->hdisplay, m->vdisplay, in hdmi_mode_fixup()
1201 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay); in hdmi_v13_mode_apply()
1211 val = (m->hsync_start - m->hdisplay - 2); in hdmi_v13_mode_apply()
1212 val |= ((m->hsync_end - m->hdisplay - 2) << 10); in hdmi_v13_mode_apply()
1241 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay)); in hdmi_v13_mode_apply()
1243 (m->hsync_start - m->hdisplay)) << 12; in hdmi_v13_mode_apply()
1270 hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay); in hdmi_v13_mode_apply()
1271 hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay); in hdmi_v13_mode_apply()
1288 (m->hdisplay == 1280 || m->hdisplay == 1024 || m->hdisplay == 1366)) in hdmi_v14_mode_apply()
[all …]
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| /drivers/gpu/drm/virtio/ |
| D | virtgpu_display.c | 89 crtc->mode.hdisplay, in virtio_gpu_crtc_mode_set_nofb()
197 if (mode->hdisplay == XRES_DEF && mode->vdisplay == YRES_DEF) in virtio_gpu_conn_mode_valid()
199 if (mode->hdisplay <= width && mode->hdisplay >= width - 16 && in virtio_gpu_conn_mode_valid()
203 DRM_DEBUG("del mode: %dx%d\n", mode->hdisplay, mode->vdisplay); in virtio_gpu_conn_mode_valid()
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