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Searched refs:hwpwm (Results 1 – 25 of 42) sorted by relevance

12

/drivers/pwm/
Dpwm-jz4740.c41 if (pwm->hwpwm < 2) in jz4740_pwm_request()
44 jz4740_timer_start(pwm->hwpwm); in jz4740_pwm_request()
51 jz4740_timer_set_ctrl(pwm->hwpwm, 0); in jz4740_pwm_free()
53 jz4740_timer_stop(pwm->hwpwm); in jz4740_pwm_free()
61 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); in jz4740_pwm_enable()
62 jz4740_timer_enable(pwm->hwpwm); in jz4740_pwm_enable()
69 uint32_t ctrl = jz4740_timer_get_ctrl(pwm->hwpwm); in jz4740_pwm_disable()
75 jz4740_timer_set_duty(pwm->hwpwm, 0xffff); in jz4740_pwm_disable()
76 jz4740_timer_set_period(pwm->hwpwm, 0x0); in jz4740_pwm_disable()
84 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); in jz4740_pwm_disable()
[all …]
Dpwm-sun4i.c118 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && in sun4i_pwm_get_state()
122 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; in sun4i_pwm_get_state()
127 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) in sun4i_pwm_get_state()
132 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) == in sun4i_pwm_get_state()
133 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) in sun4i_pwm_get_state()
138 val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm)); in sun4i_pwm_get_state()
236 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { in sun4i_pwm_apply()
238 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); in sun4i_pwm_apply()
241 ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); in sun4i_pwm_apply()
242 ctrl |= BIT_CH(prescaler, pwm->hwpwm); in sun4i_pwm_apply()
[all …]
Dpwm-pca9685.c113 if (pwm->hwpwm >= PCA9685_MAXCHAN) { in pca9685_pwm_is_gpio()
139 regmap_read(pca->regmap, LED_N_ON_H(pwm->hwpwm), &value); in pca9685_pwm_gpio_get()
152 regmap_write(pca->regmap, LED_N_OFF_L(pwm->hwpwm), 0); in pca9685_pwm_gpio_set()
153 regmap_write(pca->regmap, LED_N_OFF_H(pwm->hwpwm), 0); in pca9685_pwm_gpio_set()
156 regmap_write(pca->regmap, LED_N_ON_H(pwm->hwpwm), on); in pca9685_pwm_gpio_set()
282 if (pwm->hwpwm >= PCA9685_MAXCHAN) in pca9685_pwm_config()
285 reg = LED_N_OFF_H(pwm->hwpwm); in pca9685_pwm_config()
294 if (pwm->hwpwm >= PCA9685_MAXCHAN) in pca9685_pwm_config()
297 reg = LED_N_OFF_L(pwm->hwpwm); in pca9685_pwm_config()
301 if (pwm->hwpwm >= PCA9685_MAXCHAN) in pca9685_pwm_config()
[all …]
Dpwm-zx.c41 static inline u32 zx_pwm_readl(struct zx_pwm_chip *zpc, unsigned int hwpwm, in zx_pwm_readl() argument
44 return readl(zpc->base + (hwpwm + 1) * 0x10 + offset); in zx_pwm_readl()
47 static inline void zx_pwm_writel(struct zx_pwm_chip *zpc, unsigned int hwpwm, in zx_pwm_writel() argument
50 writel(value, zpc->base + (hwpwm + 1) * 0x10 + offset); in zx_pwm_writel()
53 static void zx_pwm_set_mask(struct zx_pwm_chip *zpc, unsigned int hwpwm, in zx_pwm_set_mask() argument
58 data = zx_pwm_readl(zpc, hwpwm, offset); in zx_pwm_set_mask()
61 zx_pwm_writel(zpc, hwpwm, offset, data); in zx_pwm_set_mask()
73 value = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); in zx_pwm_get_state()
88 tmp = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_PERIOD); in zx_pwm_get_state()
92 tmp = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_DUTY); in zx_pwm_get_state()
[all …]
Dpwm-vt8500.c108 writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm)); in vt8500_pwm_config()
109 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_SCALAR_UPDATE); in vt8500_pwm_config()
111 writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm)); in vt8500_pwm_config()
112 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_PERIOD_UPDATE); in vt8500_pwm_config()
114 writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm)); in vt8500_pwm_config()
115 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_DUTY_UPDATE); in vt8500_pwm_config()
117 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_config()
119 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_config()
120 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE); in vt8500_pwm_config()
138 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_enable()
[all …]
Dpwm-sprd.c73 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_get_state()
85 pwm->hwpwm); in sprd_pwm_get_state()
89 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE); in sprd_pwm_get_state()
103 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE); in sprd_pwm_get_state()
108 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY); in sprd_pwm_get_state()
121 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_config()
151 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale); in sprd_pwm_config()
152 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX); in sprd_pwm_config()
153 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty); in sprd_pwm_config()
163 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_apply()
[all …]
Dpwm-bcm-iproc.c92 if (value & BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm->hwpwm))) in iproc_pwmc_get_state()
97 if (value & BIT(IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm))) in iproc_pwmc_get_state()
103 prescale = value >> IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm); in iproc_pwmc_get_state()
108 value = readl(ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); in iproc_pwmc_get_state()
112 value = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); in iproc_pwmc_get_state()
159 iproc_pwmc_disable(ip, pwm->hwpwm); in iproc_pwmc_apply()
163 value &= ~IPROC_PWM_PRESCALE_MASK(pwm->hwpwm); in iproc_pwmc_apply()
164 value |= prescale << IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm); in iproc_pwmc_apply()
168 writel(period, ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); in iproc_pwmc_apply()
169 writel(duty, ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); in iproc_pwmc_apply()
[all …]
Dpwm-stmpe.c48 pwm->hwpwm); in stmpe_24xx_pwm_enable()
52 value = ret | BIT(pwm->hwpwm); in stmpe_24xx_pwm_enable()
57 pwm->hwpwm); in stmpe_24xx_pwm_enable()
74 pwm->hwpwm); in stmpe_24xx_pwm_disable()
78 value = ret & ~BIT(pwm->hwpwm); in stmpe_24xx_pwm_disable()
83 pwm->hwpwm); in stmpe_24xx_pwm_disable()
117 pin = pwm->hwpwm; in stmpe_24xx_pwm_config()
128 pwm->hwpwm); in stmpe_24xx_pwm_config()
134 switch (pwm->hwpwm) { in stmpe_24xx_pwm_config()
153 pwm->hwpwm, duty_ns, period_ns); in stmpe_24xx_pwm_config()
[all …]
Dpwm-twl.c83 base = pwm->hwpwm * 3; in twl_pwm_config()
107 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); in twl4030_pwm_enable()
113 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); in twl4030_pwm_enable()
137 val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); in twl4030_pwm_disable()
143 val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); in twl4030_pwm_disable()
159 if (pwm->hwpwm == 1) { in twl4030_pwm_request()
197 if (pwm->hwpwm == 1) in twl4030_pwm_free()
229 val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXS | TWL6030_PWMXEN); in twl6030_pwm_enable()
230 val &= ~TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXR); in twl6030_pwm_enable()
252 val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXR); in twl6030_pwm_disable()
[all …]
Dpwm-atmel.c154 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_update_cdty()
156 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); in atmel_pwm_update_cdty()
159 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_update_cdty()
169 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_set_cprd_cdty()
171 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_set_cprd_cdty()
188 while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) && in atmel_pwm_disable()
195 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm); in atmel_pwm_disable()
203 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) && in atmel_pwm_disable()
226 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, in atmel_pwm_apply()
254 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_apply()
[all …]
Dpwm-lpc32xx.c54 val = readl(lpc32xx->base + (pwm->hwpwm << 2)); in lpc32xx_pwm_config()
57 writel(val, lpc32xx->base + (pwm->hwpwm << 2)); in lpc32xx_pwm_config()
72 val = readl(lpc32xx->base + (pwm->hwpwm << 2)); in lpc32xx_pwm_enable()
74 writel(val, lpc32xx->base + (pwm->hwpwm << 2)); in lpc32xx_pwm_enable()
84 val = readl(lpc32xx->base + (pwm->hwpwm << 2)); in lpc32xx_pwm_disable()
86 writel(val, lpc32xx->base + (pwm->hwpwm << 2)); in lpc32xx_pwm_disable()
130 val = readl(lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2)); in lpc32xx_pwm_probe()
132 writel(val, lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2)); in lpc32xx_pwm_probe()
Dpwm-bcm2835.c44 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
45 value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
57 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_free()
81 pc->base + DUTY(pwm->hwpwm)); in bcm2835_pwm_config()
82 writel(period, pc->base + PERIOD(pwm->hwpwm)); in bcm2835_pwm_config()
93 value |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm); in bcm2835_pwm_enable()
105 value &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_disable()
118 value &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_set_polarity()
120 value |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm); in bcm2835_set_polarity()
Dpwm-berlin.c115 value = berlin_pwm_readl(pwm, pwm_dev->hwpwm, BERLIN_PWM_CONTROL); in berlin_pwm_config()
120 berlin_pwm_writel(pwm, pwm_dev->hwpwm, value, BERLIN_PWM_CONTROL); in berlin_pwm_config()
122 berlin_pwm_writel(pwm, pwm_dev->hwpwm, duty, BERLIN_PWM_DUTY); in berlin_pwm_config()
123 berlin_pwm_writel(pwm, pwm_dev->hwpwm, period, BERLIN_PWM_TCNT); in berlin_pwm_config()
135 value = berlin_pwm_readl(pwm, pwm_dev->hwpwm, BERLIN_PWM_CONTROL); in berlin_pwm_set_polarity()
142 berlin_pwm_writel(pwm, pwm_dev->hwpwm, value, BERLIN_PWM_CONTROL); in berlin_pwm_set_polarity()
152 value = berlin_pwm_readl(pwm, pwm_dev->hwpwm, BERLIN_PWM_EN); in berlin_pwm_enable()
154 berlin_pwm_writel(pwm, pwm_dev->hwpwm, value, BERLIN_PWM_EN); in berlin_pwm_enable()
165 value = berlin_pwm_readl(pwm, pwm_dev->hwpwm, BERLIN_PWM_EN); in berlin_pwm_disable()
167 berlin_pwm_writel(pwm, pwm_dev->hwpwm, value, BERLIN_PWM_EN); in berlin_pwm_disable()
Dpwm-atmel-tcb.c79 unsigned group = pwm->hwpwm / 2; in atmel_tcb_pwm_request()
80 unsigned index = pwm->hwpwm % 2; in atmel_tcb_pwm_request()
125 tcbpwmc->pwms[pwm->hwpwm] = tcbpwm; in atmel_tcb_pwm_request()
136 clk_disable_unprepare(tc->clk[pwm->hwpwm / 2]); in atmel_tcb_pwm_free()
137 tcbpwmc->pwms[pwm->hwpwm] = NULL; in atmel_tcb_pwm_free()
147 unsigned group = pwm->hwpwm / 2; in atmel_tcb_pwm_disable()
148 unsigned index = pwm->hwpwm % 2; in atmel_tcb_pwm_disable()
206 unsigned group = pwm->hwpwm / 2; in atmel_tcb_pwm_enable()
207 unsigned index = pwm->hwpwm % 2; in atmel_tcb_pwm_enable()
288 unsigned group = pwm->hwpwm / 2; in atmel_tcb_pwm_config()
[all …]
Dpwm-hibvt.c87 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_enable()
95 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_disable()
110 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm), in hibvt_pwm_config()
113 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm), in hibvt_pwm_config()
124 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_set_polarity()
127 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_set_polarity()
141 value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm)); in hibvt_pwm_get_state()
144 value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm)); in hibvt_pwm_get_state()
147 value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm)); in hibvt_pwm_get_state()
Dpwm-mediatek.c83 ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]); in pwm_mediatek_clk_enable()
102 clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]); in pwm_mediatek_clk_disable()
136 do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm])); in pwm_mediatek_config()
152 if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) { in pwm_mediatek_config()
162 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); in pwm_mediatek_config()
163 pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period); in pwm_mediatek_config()
164 pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty); in pwm_mediatek_config()
182 value |= BIT(pwm->hwpwm); in pwm_mediatek_enable()
194 value &= ~BIT(pwm->hwpwm); in pwm_mediatek_disable()
Dpwm-spear.c128 spear_pwm_writel(pc, pwm->hwpwm, PWMCR, in spear_pwm_config()
130 spear_pwm_writel(pc, pwm->hwpwm, PWMDCR, dc); in spear_pwm_config()
131 spear_pwm_writel(pc, pwm->hwpwm, PWMPCR, pv); in spear_pwm_config()
147 val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR); in spear_pwm_enable()
149 spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val); in spear_pwm_enable()
159 val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR); in spear_pwm_disable()
161 spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val); in spear_pwm_disable()
Dpwm-sti.c191 ((ncfg == 1) && (pwm->hwpwm == cur->hwpwm)) || in sti_pwm_config()
192 ((ncfg == 1) && (pwm->hwpwm != cur->hwpwm) && period_same) || in sti_pwm_config()
229 ret = regmap_write(pc->regmap, PWM_OUT_VAL(pwm->hwpwm), value); in sti_pwm_config()
235 set_bit(pwm->hwpwm, &pc->configured); in sti_pwm_config()
274 pwm->hwpwm, ret); in sti_pwm_enable()
309 clear_bit(pwm->hwpwm, &pc->configured); in sti_pwm_free()
323 if (pwm->hwpwm >= cdata->cpt_num_devs) { in sti_pwm_capture()
324 dev_err(dev, "device %u is not valid\n", pwm->hwpwm); in sti_pwm_capture()
332 regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_RISING); in sti_pwm_capture()
333 regmap_field_write(pc->pwm_cpt_int_en, BIT(pwm->hwpwm)); in sti_pwm_capture()
[all …]
Dpwm-fsl-ftm.c97 regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16), in fsl_pwm_request()
98 BIT(pwm->hwpwm + 16)); in fsl_pwm_request()
111 regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16), in fsl_pwm_free()
222 if (~(val | BIT(pwm->hwpwm)) & 0xFF) in fsl_pwm_is_other_pwm_enabled()
255 pwm->hwpwm); in fsl_pwm_apply_config()
285 regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm), in fsl_pwm_apply_config()
287 regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty); in fsl_pwm_apply_config()
291 reg_polarity = BIT(pwm->hwpwm); in fsl_pwm_apply_config()
293 regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity); in fsl_pwm_apply_config()
321 BIT(pwm->hwpwm), BIT(pwm->hwpwm)); in fsl_pwm_apply()
[all …]
Dpwm-samsung.c219 if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) { in pwm_samsung_request()
222 pwm->hwpwm); in pwm_samsung_request()
243 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); in pwm_samsung_enable()
259 our_chip->disabled_mask &= ~BIT(pwm->hwpwm); in pwm_samsung_enable()
269 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); in pwm_samsung_disable()
279 our_chip->disabled_mask |= BIT(pwm->hwpwm); in pwm_samsung_disable()
287 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); in pwm_samsung_manual_update()
318 tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm)); in __pwm_samsung_config()
319 oldtcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm)); in __pwm_samsung_config()
334 tin_rate = pwm_samsung_calc_tin(our_chip, pwm->hwpwm, period); in __pwm_samsung_config()
[all …]
Dpwm-stm32.c119 dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3; in stm32_pwm_raw_capture()
120 ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E; in stm32_pwm_raw_capture()
121 ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3; in stm32_pwm_raw_capture()
209 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, in stm32_pwm_capture()
210 TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ? in stm32_pwm_capture()
215 regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ? in stm32_pwm_capture()
216 TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ? in stm32_pwm_capture()
263 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, in stm32_pwm_capture()
309 regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0); in stm32_pwm_capture()
452 stm32_pwm_disable(priv, pwm->hwpwm); in stm32_pwm_apply()
[all …]
Dsysfs.c288 dev_set_name(&export->child, "pwm%u", pwm->hwpwm); in pwm_export_child()
297 pwm_prop[0] = kasprintf(GFP_KERNEL, "EXPORT=pwm%u", pwm->hwpwm); in pwm_export_child()
322 pwm_prop[0] = kasprintf(GFP_KERNEL, "UNEXPORT=pwm%u", pwm->hwpwm); in pwm_unexport_child()
341 unsigned int hwpwm; in export_store() local
344 ret = kstrtouint(buf, 0, &hwpwm); in export_store()
348 if (hwpwm >= chip->npwm) in export_store()
351 pwm = pwm_request_from_chip(chip, hwpwm, "sysfs"); in export_store()
368 unsigned int hwpwm; in unexport_store() local
371 ret = kstrtouint(buf, 0, &hwpwm); in unexport_store()
375 if (hwpwm >= chip->npwm) in unexport_store()
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Dpwm-lp3943.c34 lp3943_pwm_request_map(struct lp3943_pwm *lp3943_pwm, int hwpwm) in lp3943_pwm_request_map() argument
45 pwm_map->output = pdata->pwms[hwpwm]->output; in lp3943_pwm_request_map()
46 pwm_map->num_outputs = pdata->pwms[hwpwm]->num_outputs; in lp3943_pwm_request_map()
66 pwm_map = lp3943_pwm_request_map(lp3943_pwm, pwm->hwpwm); in lp3943_pwm_request()
113 if (pwm->hwpwm == 0) { in lp3943_pwm_config()
159 if (pwm->hwpwm == 0) in lp3943_pwm_enable()
Dpwm-tegra.c123 pwm_writel(pc, pwm->hwpwm, val); in tegra_pwm_config()
144 val = pwm_readl(pc, pwm->hwpwm); in tegra_pwm_enable()
146 pwm_writel(pc, pwm->hwpwm, val); in tegra_pwm_enable()
156 val = pwm_readl(pc, pwm->hwpwm); in tegra_pwm_disable()
158 pwm_writel(pc, pwm->hwpwm, val); in tegra_pwm_disable()
/drivers/staging/greybus/
Dpwm.c194 return gb_pwm_activate_operation(pwmc, pwm->hwpwm); in gb_pwm_request()
204 gb_pwm_deactivate_operation(pwmc, pwm->hwpwm); in gb_pwm_free()
212 return gb_pwm_config_operation(pwmc, pwm->hwpwm, duty_ns, period_ns); in gb_pwm_config()
220 return gb_pwm_set_polarity_operation(pwmc, pwm->hwpwm, polarity); in gb_pwm_set_polarity()
227 return gb_pwm_enable_operation(pwmc, pwm->hwpwm); in gb_pwm_enable()
234 gb_pwm_disable_operation(pwmc, pwm->hwpwm); in gb_pwm_disable()

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