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Searched refs:hwss (Results 1 – 18 of 18) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c481 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); in dcn20_plane_atomic_disable()
489 dc->hwss.set_flip_control_gsl(pipe_ctx, false); in dcn20_plane_atomic_disable()
498 dc->hwss.plane_atomic_power_down(dc, in dcn20_plane_atomic_disable()
588 dc->hwss.blank_pixel_data(dc, pipe_ctx, true); in dcn20_enable_stream_timing()
1020 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); in dcn20_program_pipe()
1029 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); in dcn20_program_pipe()
1050 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank); in dcn20_program_all_pipe_in_tree()
1052 if (dc->hwss.update_odm) in dcn20_program_all_pipe_in_tree()
1053 dc->hwss.update_odm(dc, context, pipe_ctx); in dcn20_program_all_pipe_in_tree()
1190 dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true); in dcn20_apply_ctx_for_surface()
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/drivers/gpu/drm/amd/display/dc/core/
Ddc_stream.c307 core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true); in dc_stream_set_cursor_attributes()
310 core_dc->hwss.set_cursor_attribute(pipe_ctx); in dc_stream_set_cursor_attributes()
311 if (core_dc->hwss.set_cursor_sdr_white_level) in dc_stream_set_cursor_attributes()
312 core_dc->hwss.set_cursor_sdr_white_level(pipe_ctx); in dc_stream_set_cursor_attributes()
316 core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false); in dc_stream_set_cursor_attributes()
358 core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true); in dc_stream_set_cursor_position()
361 core_dc->hwss.set_cursor_position(pipe_ctx); in dc_stream_set_cursor_position()
365 core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false); in dc_stream_set_cursor_position()
414 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) { in dc_stream_add_writeback()
420 if (dc->hwss.enable_writeback) { in dc_stream_add_writeback()
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Ddc.c291 dc->hwss.set_drr(&pipe, in dc_stream_adjust_vmin_vmax()
319 dc->hwss.get_position(&pipe, 1, &position); in dc_stream_get_crtc_position()
462 dc->hwss.program_gamut_remap(pipes); in dc_stream_set_gamut_remap()
481 dc->hwss.program_output_csc(dc, in dc_stream_program_csc_matrix()
515 dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events); in dc_stream_set_static_screen_events()
768 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context); in disable_dangling_plane()
793 dc->hwss.init_hw(dc); in dc_create()
858 dc->hwss.enable_per_frame_crtc_position_reset( in enable_timing_multisync()
943 dc->hwss.enable_timing_synchronization( in program_timing_sync()
1041 dc->hwss.setup_stereo) in dc_enable_stereo()
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Ddc_vm_helper.c42 if (dc->hwss.init_sys_ctx) { in dc_setup_system_context()
43 num_vmids = dc->hwss.init_sys_ctx(dc->hwseq, dc, pa_config); in dc_setup_system_context()
57 dc->hwss.init_vm_ctx(dc->hwseq, dc, va_config, vmid); in dc_setup_vm_context()
Ddc_link_hwss.c185 link->dc->hwss.edp_power_control(link, false); in dp_disable_link_phy()
293 link->dc->hwss.disable_stream(&pipes[i]); in dp_retrain_link_dp_test()
320 link->dc->hwss.enable_stream(&pipes[i]); in dp_retrain_link_dp_test()
322 link->dc->hwss.unblank_stream(&pipes[i], in dp_retrain_link_dp_test()
Ddc_link.c224 link->dc->hwss.edp_power_control(link, true); in dc_link_detect_sink()
225 link->dc->hwss.edp_wait_for_hpd_ready(link, true); in dc_link_detect_sink()
1489 link->dc->hwss.edp_power_control(link, true); in enable_link_dp()
1490 link->dc->hwss.edp_wait_for_hpd_ready(link, true); in enable_link_dp()
2727 core_dc->hwss.update_info_frame(pipe_ctx); in core_link_enable_stream()
2764 core_dc->hwss.enable_audio_stream(pipe_ctx); in core_link_enable_stream()
2788 core_dc->hwss.enable_stream(pipe_ctx); in core_link_enable_stream()
2802 core_dc->hwss.unblank_stream(pipe_ctx, in core_link_enable_stream()
2824 core_dc->hwss.blank_stream(pipe_ctx); in core_link_disable_stream()
2853 core_dc->hwss.disable_stream(pipe_ctx); in core_link_disable_stream()
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Ddc_surface.c180 core_dc->hwss.update_pending_status(pipe_ctx); in dc_plane_get_status()
Ddc_link_dp.c3212 link->dc->hwss.unblank_stream( in dc_link_dp_set_test_pattern()
/drivers/gpu/drm/amd/display/dc/dce80/
Ddce80_hw_sequencer.c77 dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating; in dce80_hw_sequencer_construct()
78 dc->hwss.pipe_control_lock = dce_pipe_control_lock; in dce80_hw_sequencer_construct()
79 dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth; in dce80_hw_sequencer_construct()
80 dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth; in dce80_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c608 hws->ctx->dc->hwss.dpp_pg_control(hws, plane_id, true); in power_on_plane()
609 hws->ctx->dc->hwss.hubp_pg_control(hws, plane_id, true); in power_on_plane()
630 dc->hwss.hubp_pg_control(hws, 0, false); in undo_DEGVIDCN10_253_wa()
659 dc->hwss.hubp_pg_control(hws, 0, true); in apply_DEGVIDCN10_253_wa()
721 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx); in false_optc_underflow_wa()
833 dc->hwss.disable_audio_stream(pipe_ctx); in dcn10_reset_back_end_for_pipe()
1016 dc->hwss.dpp_pg_control(hws, dpp->inst, false); in dcn10_plane_atomic_power_down()
1017 dc->hwss.hubp_pg_control(hws, hubp->inst, false); in dcn10_plane_atomic_power_down()
1035 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); in dcn10_plane_atomic_disable()
1049 dc->hwss.plane_atomic_power_down(dc, in dcn10_plane_atomic_disable()
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/drivers/gpu/drm/amd/display/dc/dce100/
Ddce100_hw_sequencer.c139 dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating; in dce100_hw_sequencer_construct()
140 dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth; in dce100_hw_sequencer_construct()
141 dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth; in dce100_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c670 link->dc->hwss.update_info_frame(pipe_ctx); in dce110_enable_stream()
1043 dc->hwss.disable_audio_stream(pipe_ctx); in dce110_disable_stream()
1067 link->dc->hwss.edp_backlight_control(link, true); in dce110_unblank_stream()
1077 link->dc->hwss.edp_backlight_control(link, false); in dce110_blank_stream()
1336 if (dc->hwss.disable_stream_gating) { in apply_single_controller_ctx_to_hw()
1337 dc->hwss.disable_stream_gating(dc, pipe_ctx); in apply_single_controller_ctx_to_hw()
1367 dc->hwss.enable_stream_timing(pipe_ctx, context, dc); in apply_single_controller_ctx_to_hw()
1369 if (dc->hwss.setup_vupdate_interrupt) in apply_single_controller_ctx_to_hw()
1370 dc->hwss.setup_vupdate_interrupt(pipe_ctx); in apply_single_controller_ctx_to_hw()
1515 dc->hwss.disable_plane(dc, in disable_vga_and_power_gate_all_controllers()
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Ddce110_resource.c1074 dc->hwss.enable_display_power_gating( in dce110_acquire_underlay()
/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_hw_sequencer.c268 dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating; in dce120_hw_sequencer_construct()
269 dc->hwss.update_dchub = dce120_update_dchub; in dce120_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_debugfs.c978 if (!dc->hwss.log_hw_state) in dtn_log_read()
981 dc->hwss.log_hw_state(dc, &log_ctx); in dtn_log_read()
1016 if (dc->hwss.log_hw_state) in dtn_log_write()
1017 dc->hwss.log_hw_state(dc, NULL); in dtn_log_write()
/drivers/gpu/drm/amd/display/dc/dce112/
Ddce112_hw_sequencer.c161 dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating; in dce112_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/
Ddc.h494 struct hw_sequencer_funcs hwss; member
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_hwseq.h822 void dce_enable_fe_clock(struct dce_hwseq *hwss,