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Searched refs:io_base (Results 1 – 25 of 137) sorted by relevance

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/drivers/staging/vt6655/
Dmac.c62 void __iomem *io_base = priv->PortOffset; in MACbIsRegBitsOff() local
64 return !(ioread8(io_base + byRegOfs) & byTestBits); in MACbIsRegBitsOff()
82 void __iomem *io_base = priv->PortOffset; in MACbIsIntDisable() local
84 if (ioread32(io_base + MAC_REG_IMR)) in MACbIsIntDisable()
107 void __iomem *io_base = priv->PortOffset; in MACvSetShortRetryLimit() local
109 iowrite8(byRetryLimit, io_base + MAC_REG_SRT); in MACvSetShortRetryLimit()
129 void __iomem *io_base = priv->PortOffset; in MACvSetLongRetryLimit() local
131 iowrite8(byRetryLimit, io_base + MAC_REG_LRT); in MACvSetLongRetryLimit()
150 void __iomem *io_base = priv->PortOffset; in MACvSetLoopbackMode() local
154 iowrite8((ioread8(io_base + MAC_REG_TEST) & 0x3f) | byLoopbackMode, in MACvSetLoopbackMode()
[all …]
/drivers/gpu/drm/meson/
Dmeson_viu.c83 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
85 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
87 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF00_01)); in meson_viu_set_g12a_osd1_matrix()
89 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF02_10)); in meson_viu_set_g12a_osd1_matrix()
91 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12)); in meson_viu_set_g12a_osd1_matrix()
93 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21)); in meson_viu_set_g12a_osd1_matrix()
95 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22)); in meson_viu_set_g12a_osd1_matrix()
98 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
100 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
103 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL)); in meson_viu_set_g12a_osd1_matrix()
[all …]
Dmeson_venc.c1042 priv->io_base + _REG(VENC_VDAC_SETTING)); in meson_venc_hdmi_mode_set()
1044 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in meson_venc_hdmi_mode_set()
1045 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in meson_venc_hdmi_mode_set()
1053 priv->io_base + _REG(ENCI_CFILT_CTRL)); in meson_venc_hdmi_mode_set()
1056 priv->io_base + _REG(ENCI_CFILT_CTRL2)); in meson_venc_hdmi_mode_set()
1059 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); in meson_venc_hdmi_mode_set()
1062 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE)); in meson_venc_hdmi_mode_set()
1063 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); in meson_venc_hdmi_mode_set()
1067 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN)); in meson_venc_hdmi_mode_set()
1069 priv->io_base + _REG(ENCI_SYNC_HSO_END)); in meson_venc_hdmi_mode_set()
[all …]
Dmeson_crtc.c90 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END)); in meson_g12a_crtc_atomic_enable()
95 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); in meson_g12a_crtc_atomic_enable()
99 priv->io_base + _REG(VPP_OSD1_BLD_H_SCOPE)); in meson_g12a_crtc_atomic_enable()
102 priv->io_base + _REG(VPP_OSD1_BLD_V_SCOPE)); in meson_g12a_crtc_atomic_enable()
105 priv->io_base + _REG(VPP_OUT_H_V_SIZE)); in meson_g12a_crtc_atomic_enable()
126 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); in meson_crtc_atomic_enable()
130 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END)); in meson_crtc_atomic_enable()
133 priv->io_base + _REG(VPP_MISC)); in meson_crtc_atomic_enable()
182 priv->io_base + _REG(VPP_MISC)); in meson_crtc_atomic_disable()
236 priv->io_base + _REG(VPP_MISC)); in meson_crtc_enable_osd1()
[all …]
Dmeson_vpp.c38 writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL)); in meson_vpp_setup_mux()
60 priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX)); in meson_vpp_write_scaling_filter_coefs()
63 priv->io_base + _REG(VPP_OSD_SCALE_COEF)); in meson_vpp_write_scaling_filter_coefs()
85 priv->io_base + _REG(VPP_SCALE_COEF_IDX)); in meson_vpp_write_vd_scaling_filter_coefs()
88 priv->io_base + _REG(VPP_SCALE_COEF)); in meson_vpp_write_vd_scaling_filter_coefs()
95 writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
98 priv->io_base + _REG(VIU_MISC_CTRL1)); in meson_vpp_init()
100 priv->io_base + _REG(VPP_DOLBY_CTRL)); in meson_vpp_init()
102 priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
104 writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL)); in meson_vpp_init()
[all …]
/drivers/watchdog/
Dni903x_wdt.c40 u16 io_base; member
58 u8 control = inb(wdt->io_base + NIWD_CONTROL); in ni903x_start()
60 outb(control | NIWD_CONTROL_RESET, wdt->io_base + NIWD_CONTROL); in ni903x_start()
61 outb(control | NIWD_CONTROL_PET, wdt->io_base + NIWD_CONTROL); in ni903x_start()
70 outb(((0x00FF0000 & counter) >> 16), wdt->io_base + NIWD_SEED2); in ni903x_wdd_set_timeout()
71 outb(((0x0000FF00 & counter) >> 8), wdt->io_base + NIWD_SEED1); in ni903x_wdd_set_timeout()
72 outb((0x000000FF & counter), wdt->io_base + NIWD_SEED0); in ni903x_wdd_set_timeout()
85 control = inb(wdt->io_base + NIWD_CONTROL); in ni903x_wdd_get_timeleft()
87 outb(control, wdt->io_base + NIWD_CONTROL); in ni903x_wdd_get_timeleft()
89 counter2 = inb(wdt->io_base + NIWD_COUNTER2); in ni903x_wdd_get_timeleft()
[all …]
Dnic7018_wdt.c46 u16 io_base; member
96 wdt->io_base + WDT_PRESET_PRESCALE); in nic7018_set_timeout()
111 control = inb(wdt->io_base + WDT_RELOAD_CTRL); in nic7018_start()
112 outb(control | WDT_RELOAD_PORT_EN, wdt->io_base + WDT_RELOAD_CTRL); in nic7018_start()
114 outb(1, wdt->io_base + WDT_RELOAD_PORT); in nic7018_start()
116 control = inb(wdt->io_base + WDT_CTRL); in nic7018_start()
117 outb(control | WDT_CTRL_RESET_EN, wdt->io_base + WDT_CTRL); in nic7018_start()
126 outb(0, wdt->io_base + WDT_CTRL); in nic7018_stop()
127 outb(0, wdt->io_base + WDT_RELOAD_CTRL); in nic7018_stop()
128 outb(0xF0, wdt->io_base + WDT_PRESET_PRESCALE); in nic7018_stop()
[all …]
/drivers/fpga/
Dts73xx-fpga.c31 void __iomem *io_base; member
47 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
49 writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
64 ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG, in ts73xx_fpga_write()
70 writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG); in ts73xx_fpga_write()
84 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
86 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
89 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
91 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
93 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
[all …]
Dxilinx-pr-decoupler.c22 void __iomem *io_base; member
29 writel(val, d->io_base + offset); in xlnx_pr_decoupler_write()
35 return readl(d->io_base + offset); in xlnx_pr_decouple_read()
67 status = readl(priv->io_base); in xlnx_pr_decoupler_enable_show()
98 priv->io_base = devm_ioremap_resource(&pdev->dev, res); in xlnx_pr_decoupler_probe()
99 if (IS_ERR(priv->io_base)) in xlnx_pr_decoupler_probe()
100 return PTR_ERR(priv->io_base); in xlnx_pr_decoupler_probe()
/drivers/hwspinlock/
Du8500_hsem.c92 void __iomem *io_base; in u8500_hsem_probe() local
103 io_base = ioremap(res->start, resource_size(res)); in u8500_hsem_probe()
104 if (!io_base) in u8500_hsem_probe()
108 val = readl(io_base + HSEM_CTRL_REG); in u8500_hsem_probe()
109 writel((val & ~HSEM_PROTOCOL_1), io_base + HSEM_CTRL_REG); in u8500_hsem_probe()
112 writel(0xFFFF, io_base + HSEM_ICRALL); in u8500_hsem_probe()
123 hwlock->priv = io_base + HSEM_REGISTER_OFFSET + sizeof(u32) * i; in u8500_hsem_probe()
139 iounmap(io_base); in u8500_hsem_probe()
146 void __iomem *io_base = bank->lock[0].priv - HSEM_REGISTER_OFFSET; in u8500_hsem_remove() local
150 writel(0xFFFF, io_base + HSEM_ICRALL); in u8500_hsem_remove()
[all …]
Domap_hwspinlock.c80 void __iomem *io_base; in omap_hwspinlock_probe() local
92 io_base = ioremap(res->start, resource_size(res)); in omap_hwspinlock_probe()
93 if (!io_base) in omap_hwspinlock_probe()
108 i = readl(io_base + SYSSTATUS_OFFSET); in omap_hwspinlock_probe()
136 hwlock->priv = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i; in omap_hwspinlock_probe()
152 iounmap(io_base); in omap_hwspinlock_probe()
159 void __iomem *io_base = bank->lock[0].priv - LOCK_BASE_OFFSET; in omap_hwspinlock_remove() local
169 iounmap(io_base); in omap_hwspinlock_remove()
Dsirf_hwspinlock.c23 void __iomem *io_base; member
72 hwspin->io_base = of_iomap(pdev->dev.of_node, 0); in sirf_hwspinlock_probe()
73 if (!hwspin->io_base) in sirf_hwspinlock_probe()
78 hwlock->priv = hwspin->io_base + HW_SPINLOCK_OFFSET(idx); in sirf_hwspinlock_probe()
95 iounmap(hwspin->io_base); in sirf_hwspinlock_probe()
113 iounmap(hwspin->io_base); in sirf_hwspinlock_remove()
/drivers/spi/
Dspi-stm32-qspi.c101 void __iomem *io_base; member
129 sr = readl_relaxed(qspi->io_base + QSPI_SR); in stm32_qspi_irq()
133 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_irq()
135 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
170 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, in stm32_qspi_tx_poll()
178 tx_fifo(buf++, qspi->io_base + QSPI_DR); in stm32_qspi_tx_poll()
233 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
245 writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
256 writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
282 return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr, in stm32_qspi_wait_nobusy()
[all …]
/drivers/mtd/nand/raw/
Dlpc32xx_slc.c221 void __iomem *io_base; member
243 writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base)); in lpc32xx_nand_setup()
247 writel(0, SLC_CFG(host->io_base)); in lpc32xx_nand_setup()
248 writel(0, SLC_IEN(host->io_base)); in lpc32xx_nand_setup()
250 SLC_ICR(host->io_base)); in lpc32xx_nand_setup()
266 writel(tmp, SLC_TAC(host->io_base)); in lpc32xx_nand_setup()
279 tmp = readl(SLC_CFG(host->io_base)); in lpc32xx_nand_cmd_ctrl()
284 writel(tmp, SLC_CFG(host->io_base)); in lpc32xx_nand_cmd_ctrl()
288 writel(cmd, SLC_CMD(host->io_base)); in lpc32xx_nand_cmd_ctrl()
290 writel(cmd, SLC_ADDR(host->io_base)); in lpc32xx_nand_cmd_ctrl()
[all …]
Dlpc32xx_mlc.c181 void __iomem *io_base; member
237 writel(MLCCMD_RESET, MLC_CMD(host->io_base)); in lpc32xx_nand_setup()
247 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base)); in lpc32xx_nand_setup()
251 writel(tmp, MLC_ICR(host->io_base)); in lpc32xx_nand_setup()
255 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base)); in lpc32xx_nand_setup()
266 writel(tmp, MLC_TIME_REG(host->io_base)); in lpc32xx_nand_setup()
270 MLC_IRQ_MR(host->io_base)); in lpc32xx_nand_setup()
273 writel(MLCCEH_NORMAL, MLC_CEH(host->io_base)); in lpc32xx_nand_setup()
286 writel(cmd, MLC_CMD(host->io_base)); in lpc32xx_nand_cmd_ctrl()
288 writel(cmd, MLC_ADDR(host->io_base)); in lpc32xx_nand_cmd_ctrl()
[all …]
Dsocrates_nand.c26 void __iomem *io_base; member
43 out_be32(host->io_base, FPGA_NAND_ENABLE | in socrates_nand_write_buf()
64 out_be32(host->io_base, val); in socrates_nand_read_buf()
66 buf[i] = (in_be32(host->io_base) >> in socrates_nand_read_buf()
104 out_be32(host->io_base, val); in socrates_nand_cmd_ctrl()
114 if (in_be32(host->io_base) & FPGA_NAND_BUSY) in socrates_nand_device_ready()
134 host->io_base = of_iomap(ofdev->dev.of_node, 0); in socrates_nand_probe()
135 if (host->io_base == NULL) { in socrates_nand_probe()
175 iounmap(host->io_base); in socrates_nand_probe()
188 iounmap(host->io_base); in socrates_nand_remove()
Dorion_nand.c53 void __iomem *io_base = chip->legacy.IO_ADDR_R; in orion_nand_read_buf() local
60 *buf++ = readb(io_base); in orion_nand_read_buf()
73 asm volatile ("ldrd\t%0, [%1]" : "=&r" (x) : "r" (io_base)); in orion_nand_read_buf()
78 readsl(io_base, buf, len/4); in orion_nand_read_buf()
82 buf[i++] = readb(io_base); in orion_nand_read_buf()
92 void __iomem *io_base; in orion_nand_probe() local
105 io_base = devm_ioremap_resource(&pdev->dev, res); in orion_nand_probe()
107 if (IS_ERR(io_base)) in orion_nand_probe()
108 return PTR_ERR(io_base); in orion_nand_probe()
139 nc->legacy.IO_ADDR_R = nc->legacy.IO_ADDR_W = io_base; in orion_nand_probe()
Doxnas_nand.c32 void __iomem *io_base; member
41 return readb(oxnas->io_base); in oxnas_nand_read_byte()
48 ioread8_rep(oxnas->io_base, buf, len); in oxnas_nand_read_buf()
56 iowrite8_rep(oxnas->io_base, buf, len); in oxnas_nand_write_buf()
66 writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_CLE); in oxnas_nand_cmd_ctrl()
68 writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_ALE); in oxnas_nand_cmd_ctrl()
95 oxnas->io_base = devm_ioremap_resource(&pdev->dev, res); in oxnas_nand_probe()
96 if (IS_ERR(oxnas->io_base)) in oxnas_nand_probe()
97 return PTR_ERR(oxnas->io_base); in oxnas_nand_probe()
Dstm32_fmc2_nand.c254 void __iomem *io_base; member
290 u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR); in stm32_fmc2_timings_init()
311 writel_relaxed(pcr, fmc2->io_base + FMC2_PCR); in stm32_fmc2_timings_init()
312 writel_relaxed(pmem, fmc2->io_base + FMC2_PMEM); in stm32_fmc2_timings_init()
313 writel_relaxed(patt, fmc2->io_base + FMC2_PATT); in stm32_fmc2_timings_init()
320 u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR); in stm32_fmc2_setup()
341 writel_relaxed(pcr, fmc2->io_base + FMC2_PCR); in stm32_fmc2_setup()
413 u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR); in stm32_fmc2_set_buswidth_16()
418 writel_relaxed(pcr, fmc2->io_base + FMC2_PCR); in stm32_fmc2_set_buswidth_16()
424 u32 pcr = readl(fmc2->io_base + FMC2_PCR); in stm32_fmc2_set_ecc()
[all …]
/drivers/mtd/devices/
Dspear_smi.c174 void __iomem *io_base; member
229 ctrlreg1 = readl(dev->io_base + SMI_CR1); in spear_smi_read_sr()
231 writel(ctrlreg1 & ~(SW_MODE | WB_MODE), dev->io_base + SMI_CR1); in spear_smi_read_sr()
235 dev->io_base + SMI_CR2); in spear_smi_read_sr()
248 writel(ctrlreg1, dev->io_base + SMI_CR1); in spear_smi_read_sr()
249 writel(0, dev->io_base + SMI_CR2); in spear_smi_read_sr()
301 status = readl(dev->io_base + SMI_SR); in spear_smi_int_handler()
307 writel(0, dev->io_base + SMI_SR); in spear_smi_int_handler()
343 writel(0, dev->io_base + SMI_SR); in spear_smi_hw_init()
345 writel(val, dev->io_base + SMI_CR1); in spear_smi_hw_init()
[all …]
/drivers/mtd/spi-nor/
Dnxp-spifi.c57 void __iomem *io_base; member
69 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_wait_for_cmd()
82 writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT); in nxp_spifi_reset()
83 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_reset()
115 writel(spifi->mcmd, spifi->io_base + SPIFI_MCMD); in nxp_spifi_set_memory_mode_on()
116 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_set_memory_mode_on()
140 writel(cmd, spifi->io_base + SPIFI_CMD); in nxp_spifi_read_reg()
143 *buf++ = readb(spifi->io_base + SPIFI_DATA); in nxp_spifi_read_reg()
163 writel(cmd, spifi->io_base + SPIFI_CMD); in nxp_spifi_write_reg()
166 writeb(*buf++, spifi->io_base + SPIFI_DATA); in nxp_spifi_write_reg()
[all …]
/drivers/input/keyboard/
Dspear-keyboard.c57 void __iomem *io_base; member
76 sts = readl_relaxed(kbd->io_base + STATUS_REG); in spear_kbd_interrupt()
86 val = readl_relaxed(kbd->io_base + DATA_REG) & in spear_kbd_interrupt()
97 writel_relaxed(0, kbd->io_base + STATUS_REG); in spear_kbd_interrupt()
121 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
122 writel_relaxed(1, kbd->io_base + STATUS_REG); in spear_kbd_open()
125 val = readl_relaxed(kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
127 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
138 val = readl_relaxed(kbd->io_base + MODE_CTL_REG); in spear_kbd_close()
140 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_close()
[all …]
/drivers/net/ethernet/hisilicon/hns3/
Dhns3_debugfs.c58 base_add_h = readl_relaxed(ring->tqp->io_base + in hns3_dbg_queue_info()
60 base_add_l = readl_relaxed(ring->tqp->io_base + in hns3_dbg_queue_info()
65 value = readl_relaxed(ring->tqp->io_base + in hns3_dbg_queue_info()
69 value = readl_relaxed(ring->tqp->io_base + in hns3_dbg_queue_info()
73 value = readl_relaxed(ring->tqp->io_base + in hns3_dbg_queue_info()
77 value = readl_relaxed(ring->tqp->io_base + in hns3_dbg_queue_info()
81 value = readl_relaxed(ring->tqp->io_base + in hns3_dbg_queue_info()
85 value = readl_relaxed(ring->tqp->io_base + in hns3_dbg_queue_info()
90 base_add_h = readl_relaxed(ring->tqp->io_base + in hns3_dbg_queue_info()
92 base_add_l = readl_relaxed(ring->tqp->io_base + in hns3_dbg_queue_info()
[all …]
/drivers/crypto/hisilicon/
Dqm.c323 return readl_relaxed_poll_timeout(qm->io_base + QM_MB_CMD_SEND_BASE, in qm_wait_mb_ready()
331 void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE; in qm_mb_write()
391 writeq(doorbell, qm->io_base + QM_DOORBELL_BASE_V1); in qm_db_v1()
410 writeq(doorbell, qm->io_base + dbase); in qm_db_v2()
425 writel(0x1, qm->io_base + QM_MEM_START_INIT); in qm_dev_mem_reset()
426 return readl_relaxed_poll_timeout(qm->io_base + QM_MEM_INIT_DONE, val, in qm_dev_mem_reset()
526 if (readl(qm->io_base + QM_VF_EQ_INT_SOURCE)) in qm_irq()
541 if (!readl(qm->io_base + QM_VF_AEQ_INT_SOURCE)) in qm_aeq_irq()
576 tmp = readl(qm->io_base + QM_ABNORMAL_INT_STATUS); in qm_abnormal_irq()
588 writel(error_status, qm->io_base + QM_ABNORMAL_INT_SOURCE); in qm_abnormal_irq()
[all …]
/drivers/mfd/
Dtqmx86.c165 void __iomem *io_base; in tqmx86_probe() local
186 io_base = devm_ioport_map(dev, TQMX86_IOBASE, TQMX86_IOSIZE); in tqmx86_probe()
187 if (!io_base) in tqmx86_probe()
190 board_id = ioread8(io_base + TQMX86_REG_BOARD_ID); in tqmx86_probe()
192 rev = ioread8(io_base + TQMX86_REG_BOARD_REV); in tqmx86_probe()
198 i2c_det = ioread8(io_base + TQMX86_REG_I2C_DETECT); in tqmx86_probe()
199 i2c_ien = ioread8(io_base + TQMX86_REG_I2C_INT_EN); in tqmx86_probe()
204 iowrite8(io_ext_int_val, io_base + TQMX86_REG_IO_EXT_INT); in tqmx86_probe()
205 readback = ioread8(io_base + TQMX86_REG_IO_EXT_INT); in tqmx86_probe()

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