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Searched refs:mask1 (Results 1 – 25 of 27) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/
Ddc_helper.c59 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in set_reg_field_values() argument
67 field_value1, mask1, shift1); in set_reg_field_values()
82 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in generic_reg_update_ex() argument
91 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, in generic_reg_update_ex()
105 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in generic_reg_set_ex() argument
113 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, in generic_reg_set_ex()
152 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get2() argument
156 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); in generic_reg_get2()
162 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get3() argument
167 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); in generic_reg_get3()
[all …]
Ddm_services.h136 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
140 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
/drivers/soc/fsl/qe/
Dgpio.c250 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1)); in qe_pin_set_dedicated() local
265 if (sregs->cpdata & mask1) in qe_pin_set_dedicated()
266 qe_gc->cpdata |= mask1; in qe_pin_set_dedicated()
268 qe_gc->cpdata &= ~mask1; in qe_pin_set_dedicated()
271 clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1); in qe_pin_set_dedicated()
/drivers/irqchip/
Dirq-sirfsoc.c92 u32 mask1; member
104 sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1); in sirfsoc_irq_suspend()
116 writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1); in sirfsoc_irq_resume()
/drivers/pcmcia/
Dtcic.c241 u_int mask1; in irq_scan() local
252 mask1 = 0; in irq_scan()
256 mask1 |= (1 << i); in irq_scan()
258 if ((mask1 & (1 << i)) && (try_irq(i) != 0)) { in irq_scan()
259 mask1 ^= (1 << i); in irq_scan()
263 if (mask1) { in irq_scan()
270 mask1 |= (1 << i); in irq_scan()
278 if (mask1 & (1<<i)) in irq_scan()
279 printk("%s%d", ((mask1 & ((1<<i)-1)) ? "," : ""), i); in irq_scan()
282 return mask1; in irq_scan()
Di82365.c519 u_int mask1 = 0; in isa_scan() local
533 mask1 |= (1 << i); in isa_scan()
535 if ((mask1 & (1 << i)) && (test_irq(sock, i) != 0)) in isa_scan()
536 mask1 ^= (1 << i); in isa_scan()
540 if (mask1) { in isa_scan()
546 mask1 |= (1 << i); in isa_scan()
554 if (mask1 & (1<<i)) in isa_scan()
555 printk("%s%d", ((mask1 & ((1<<i)-1)) ? "," : ""), i); in isa_scan()
556 if (mask1 == 0) printk("none!"); in isa_scan()
558 return mask1; in isa_scan()
/drivers/gpu/drm/amd/display/dc/irq/dce120/
Dirq_service_dce120.c105 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
108 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
110 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
111 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
/drivers/net/hamradio/
Dhdlcdrv.c158 unsigned int mask1, mask2, mask3, mask4, mask5, mask6, word; in hdlcdrv_receiver() local
176 for(i = 15, mask1 = 0x1fc00, mask2 = 0x1fe00, mask3 = 0x0fc00, in hdlcdrv_receiver()
179 i--, mask1 <<= 1, mask2 <<= 1, mask3 <<= 1, mask4 <<= 1, in hdlcdrv_receiver()
181 if ((s->hdlcrx.bitstream & mask1) == mask1) in hdlcdrv_receiver()
254 unsigned int mask1, mask2, mask3; in hdlcdrv_transmitter() local
329 mask1 = 0x1f000; in hdlcdrv_transmitter()
333 for(i = 0; i < 8; i++, mask1 <<= 1, mask2 <<= 1, in hdlcdrv_transmitter()
335 if ((s->hdlctx.bitstream & mask1) != mask1) in hdlcdrv_transmitter()
/drivers/gpu/drm/amd/display/dc/irq/dcn20/
Dirq_service_dcn20.c188 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
191 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
193 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
194 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn21/
Dirq_service_dcn21.c184 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
187 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
189 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
190 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn10/
Dirq_service_dcn10.c186 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
189 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
191 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
192 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h395 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
399 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
404 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
410 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
417 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
425 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
434 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
485 uint8_t shift1, uint32_t mask1, uint32_t field_value1,
/drivers/mfd/
Dmenelaus.c163 u8 mask1, mask2; member
201 the_menelaus->mask1 &= ~(1 << irq); in menelaus_enable_irq()
203 the_menelaus->mask1); in menelaus_enable_irq()
215 the_menelaus->mask1 |= (1 << irq); in menelaus_disable_irq()
217 the_menelaus->mask1); in menelaus_disable_irq()
772 & ~menelaus->mask1; in menelaus_work()
1181 menelaus->mask1 = 0xff; in menelaus_probe()
/drivers/power/supply/
Drt9455_charger.c854 unsigned int irq1, mask1, mask2; in rt9455_irq_handler_check_irq1_register() local
866 ret = regmap_read(info->regmap, RT9455_REG_MASK1, &mask1); in rt9455_irq_handler_check_irq1_register()
887 if ((mask1 & GET_MASK(F_BATABM)) == 0) { in rt9455_irq_handler_check_irq1_register()
1500 unsigned int irq1, mask1; in rt9455_batt_presence_work_callback() local
1522 ret = regmap_read(info->regmap, RT9455_REG_MASK1, &mask1); in rt9455_batt_presence_work_callback()
1528 if (mask1 & GET_MASK(F_BATABM)) { in rt9455_batt_presence_work_callback()
/drivers/gpu/drm/msm/edp/
Dedp_ctrl.c1030 u32 isr1, isr2, mask1, mask2; in msm_edp_ctrl_irq() local
1038 mask1 = isr1 & EDP_INTR_MASK1; in msm_edp_ctrl_irq()
1041 isr1 &= ~mask1; /* remove masks bit */ in msm_edp_ctrl_irq()
1045 isr1, mask1, isr2, mask2); in msm_edp_ctrl_irq()
1049 ack |= mask1; in msm_edp_ctrl_irq()
/drivers/edac/
Di5100_edac.c888 u16 mask1; in i5100_do_inject() local
911 mask1 = priv->inject_eccmask2; in i5100_do_inject()
915 pci_write_config_word(priv->mc, I5100_MEM0EINJMSK1, mask1); in i5100_do_inject()
918 pci_write_config_word(priv->mc, I5100_MEM1EINJMSK1, mask1); in i5100_do_inject()
Damd64_edac.c1039 u32 *mask1 = &pvt->csels[1].csmasks[cs]; in read_dct_base_mask() local
1048 if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1)) in read_dct_base_mask()
1050 cs, *mask1, (pvt->fam == 0x10) ? reg1 in read_dct_base_mask()
/drivers/net/ethernet/freescale/fman/
Dfman_memac.c490 u64 mask1, mask2; in get_mac_addr_hash_code() local
495 mask1 = eth_addr & (u64)0x01; in get_mac_addr_hash_code()
500 mask1 ^= mask2; in get_mac_addr_hash_code()
504 xor_val |= (mask1 << (5 - i)); in get_mac_addr_hash_code()
/drivers/acpi/
Dacpi_lpss.c942 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; in lpss_iosf_enter_d3_state() local
979 LPSS_IOSF_GPIODEF0, value1, mask1); in lpss_iosf_enter_d3_state()
991 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; in lpss_iosf_exit_d3_state() local
1003 LPSS_IOSF_GPIODEF0, value1, mask1); in lpss_iosf_exit_d3_state()
/drivers/net/can/
Dpch_can.c125 u32 mask1; member
333 iowrite32(0xffff, &priv->regs->ifregs[0].mask1); in pch_can_clear_if_buffers()
371 iowrite32(0, &priv->regs->ifregs[0].mask1); in pch_can_config_rx_tx_buffers()
394 iowrite32(0, &priv->regs->ifregs[1].mask1); in pch_can_config_rx_tx_buffers()
/drivers/usb/host/
Dr8a66597-hcd.c1607 u16 mask0, mask1, mask2; in r8a66597_irq() local
1620 mask1 = intsts1 & intenb1; in r8a66597_irq()
1642 if (mask1) { in r8a66597_irq()
1643 if (mask1 & ATTCH) { in r8a66597_irq()
1650 if (mask1 & DTCH) { in r8a66597_irq()
1655 if (mask1 & BCHG) { in r8a66597_irq()
1661 if (mask1 & SIGN) { in r8a66597_irq()
1666 if (mask1 & SACK) { in r8a66597_irq()
/drivers/iio/adc/
Dtwl6030-gpadc.c682 unsigned int reg1, unsigned int mask0, unsigned int mask1, in twl6032_get_trim_value() argument
688 val |= (trim_regs[reg1] & mask1) >> 1; in twl6032_get_trim_value()
/drivers/tty/
Dnozomi.c1031 u16 read_iir, u16 mask1, u16 mask2) in handle_data_dl() argument
1033 if (*toggle == 0 && read_iir & mask1) { in handle_data_dl()
1035 writew(mask1, dc->reg_fcr); in handle_data_dl()
1051 if (read_iir & mask1) { in handle_data_dl()
1053 writew(mask1, dc->reg_fcr); in handle_data_dl()
/drivers/clk/bcm/
Dclk-bcm2835.c439 u32 mask1; member
449 .mask1 = A2W_PLL_KI_MASK | A2W_PLL_KP_MASK,
459 .mask1 = A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK,
689 ana[1] &= ~data->ana->mask1; in bcm2835_pll_set_rate()
/drivers/staging/most/dim2/
Dhal.c561 u32 const mask1 = bit_mask(MLBC1_CLKMERR_BIT) | in dim2_is_mlb_locked() local
567 return (readl(&g.dim2->MLBC1) & mask1) == 0 && in dim2_is_mlb_locked()

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