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Searched refs:mask2 (Results 1 – 23 of 23) sorted by relevance

/drivers/gpu/drm/amd/display/dc/
Ddc_helper.c153 uint8_t shift2, uint32_t mask2, uint32_t *field_value2) in generic_reg_get2() argument
157 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get2()
163 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get3() argument
168 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get3()
175 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get4() argument
181 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get4()
189 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get5() argument
196 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get5()
205 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get6() argument
213 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get6()
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/drivers/soc/fsl/qe/
Dgpio.c251 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2); in qe_pin_set_dedicated() local
258 clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2); in qe_pin_set_dedicated()
259 clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2); in qe_pin_set_dedicated()
261 clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2); in qe_pin_set_dedicated()
262 clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2); in qe_pin_set_dedicated()
/drivers/net/wireless/ath/ath9k/
Dar9002_mac.c36 u32 mask2 = 0; in ar9002_hw_get_isr() local
67 mask2 |= ATH9K_INT_TIM; in ar9002_hw_get_isr()
69 mask2 |= ATH9K_INT_DTIM; in ar9002_hw_get_isr()
71 mask2 |= ATH9K_INT_DTIMSYNC; in ar9002_hw_get_isr()
73 mask2 |= ATH9K_INT_CABEND; in ar9002_hw_get_isr()
75 mask2 |= ATH9K_INT_GTT; in ar9002_hw_get_isr()
77 mask2 |= ATH9K_INT_CST; in ar9002_hw_get_isr()
79 mask2 |= ATH9K_INT_TSFOOR; in ar9002_hw_get_isr()
134 *masked |= mask2; in ar9002_hw_get_isr()
Dar9003_mac.c186 u32 mask2 = 0; in ar9003_hw_get_isr() local
216 mask2 |= ((isr2 & AR_ISR_S2_TIM) >> in ar9003_hw_get_isr()
218 mask2 |= ((isr2 & AR_ISR_S2_DTIM) >> in ar9003_hw_get_isr()
220 mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >> in ar9003_hw_get_isr()
222 mask2 |= ((isr2 & AR_ISR_S2_CABEND) >> in ar9003_hw_get_isr()
224 mask2 |= ((isr2 & AR_ISR_S2_GTT) << in ar9003_hw_get_isr()
226 mask2 |= ((isr2 & AR_ISR_S2_CST) << in ar9003_hw_get_isr()
228 mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >> in ar9003_hw_get_isr()
230 mask2 |= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >> in ar9003_hw_get_isr()
302 *masked |= mask2; in ar9003_hw_get_isr()
Dmac.c911 u32 mask, mask2; in ath9k_hw_set_interrupts() local
928 mask2 = 0; in ath9k_hw_set_interrupts()
972 mask2 |= AR_IMR_S2_TIM; in ath9k_hw_set_interrupts()
974 mask2 |= AR_IMR_S2_DTIM; in ath9k_hw_set_interrupts()
976 mask2 |= AR_IMR_S2_DTIMSYNC; in ath9k_hw_set_interrupts()
978 mask2 |= AR_IMR_S2_CABEND; in ath9k_hw_set_interrupts()
980 mask2 |= AR_IMR_S2_TSFOOR; in ath9k_hw_set_interrupts()
986 mask2 |= AR_IMR_S2_GTT; in ath9k_hw_set_interrupts()
988 mask2 |= AR_IMR_S2_CST; in ath9k_hw_set_interrupts()
994 mask2 |= AR_IMR_S2_BB_WATCHDOG; in ath9k_hw_set_interrupts()
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/drivers/net/hamradio/
Dbaycom_par.c206 unsigned int data, mask, mask2, descx; in par96_rx() local
235 for(mask = 0x1fe00, mask2 = 0xfc00, i = 0; in par96_rx()
236 i < PAR96_BURSTBITS; i++, mask <<= 1, mask2 <<= 1) in par96_rx()
237 if ((bc->modem.par96.dcd_shreg & mask) == mask2) in par96_rx()
240 for(mask = 0x1fe00, mask2 = 0x1fe00, i = 0; in par96_rx()
241 i < PAR96_BURSTBITS; i++, mask <<= 1, mask2 <<= 1) in par96_rx()
242 if (((bc->modem.par96.dcd_shreg & mask) == mask2) && in par96_rx()
Dhdlcdrv.c158 unsigned int mask1, mask2, mask3, mask4, mask5, mask6, word; in hdlcdrv_receiver() local
176 for(i = 15, mask1 = 0x1fc00, mask2 = 0x1fe00, mask3 = 0x0fc00, in hdlcdrv_receiver()
179 i--, mask1 <<= 1, mask2 <<= 1, mask3 <<= 1, mask4 <<= 1, in hdlcdrv_receiver()
183 else if ((s->hdlcrx.bitstream & mask2) == mask3) { in hdlcdrv_receiver()
254 unsigned int mask1, mask2, mask3; in hdlcdrv_transmitter() local
330 mask2 = 0x10000; in hdlcdrv_transmitter()
333 for(i = 0; i < 8; i++, mask1 <<= 1, mask2 <<= 1, in hdlcdrv_transmitter()
337 s->hdlctx.bitstream &= ~mask2; in hdlcdrv_transmitter()
/drivers/power/supply/
Drt9455_charger.c854 unsigned int irq1, mask1, mask2; in rt9455_irq_handler_check_irq1_register() local
896 ret = regmap_read(info->regmap, RT9455_REG_MASK2, &mask2); in rt9455_irq_handler_check_irq1_register()
902 if (mask2 & GET_MASK(F_CHTERMIM)) { in rt9455_irq_handler_check_irq1_register()
911 if (mask2 & GET_MASK(F_CHRCHGIM)) { in rt9455_irq_handler_check_irq1_register()
948 unsigned int irq2, mask2; in rt9455_irq_handler_check_irq2_register() local
959 ret = regmap_read(info->regmap, RT9455_REG_MASK2, &mask2); in rt9455_irq_handler_check_irq2_register()
989 if ((mask2 & GET_MASK(F_CHTERMIM)) == 0) { in rt9455_irq_handler_check_irq2_register()
1000 mask2 = mask2 | GET_MASK(F_CHTERMIM); in rt9455_irq_handler_check_irq2_register()
1014 if (mask2 & GET_MASK(F_CHTERMIM)) { in rt9455_irq_handler_check_irq2_register()
1022 mask2 = mask2 & ~GET_MASK(F_CHTERMIM); in rt9455_irq_handler_check_irq2_register()
/drivers/gpu/drm/amd/display/dc/irq/dce120/
Dirq_service_dce120.c105 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
115 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
117 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn20/
Dirq_service_dcn20.c188 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
198 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
200 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn21/
Dirq_service_dcn21.c184 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
194 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
196 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn10/
Dirq_service_dcn10.c186 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
196 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
198 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
/drivers/mfd/
Dmenelaus.c163 u8 mask1, mask2; member
197 the_menelaus->mask2 &= ~(1 << irq); in menelaus_enable_irq()
199 the_menelaus->mask2); in menelaus_enable_irq()
211 the_menelaus->mask2 |= (1 << irq); in menelaus_disable_irq()
213 the_menelaus->mask2); in menelaus_disable_irq()
770 & ~menelaus->mask2) << 8; in menelaus_work()
1182 menelaus->mask2 = 0xff; in menelaus_probe()
/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h396 uint8_t shift2, uint32_t mask2, uint32_t *field_value2);
400 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
405 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
411 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
418 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
426 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
435 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
/drivers/acpi/
Dacpi_lpss.c944 u32 mask2 = LPSS_PMCSR_Dx_MASK; in lpss_iosf_enter_d3_state() local
973 LPSS_IOSF_PMCSR, value2, mask2); in lpss_iosf_enter_d3_state()
976 LPSS_IOSF_PMCSR, value2, mask2); in lpss_iosf_enter_d3_state()
993 u32 mask2 = LPSS_PMCSR_Dx_MASK; in lpss_iosf_exit_d3_state() local
1006 LPSS_IOSF_PMCSR, value2, mask2); in lpss_iosf_exit_d3_state()
1009 LPSS_IOSF_PMCSR, value2, mask2); in lpss_iosf_exit_d3_state()
/drivers/gpu/drm/msm/edp/
Dedp_ctrl.c1030 u32 isr1, isr2, mask1, mask2; in msm_edp_ctrl_irq() local
1039 mask2 = isr2 & EDP_INTR_MASK2; in msm_edp_ctrl_irq()
1042 isr2 &= ~mask2; in msm_edp_ctrl_irq()
1045 isr1, mask1, isr2, mask2); in msm_edp_ctrl_irq()
1054 ack |= mask2; in msm_edp_ctrl_irq()
/drivers/net/can/
Dpch_can.c126 u32 mask2; member
334 iowrite32(0xffff, &priv->regs->ifregs[0].mask2); in pch_can_clear_if_buffers()
372 pch_can_bit_clear(&priv->regs->ifregs[0].mask2, in pch_can_config_rx_tx_buffers()
395 pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff); in pch_can_config_rx_tx_buffers()
/drivers/net/ethernet/freescale/fman/
Dfman_memac.c490 u64 mask1, mask2; in get_mac_addr_hash_code() local
499 mask2 = eth_addr & (u64)0x01; in get_mac_addr_hash_code()
500 mask1 ^= mask2; in get_mac_addr_hash_code()
/drivers/tty/
Dnozomi.c1031 u16 read_iir, u16 mask1, u16 mask2) in handle_data_dl() argument
1039 if (read_iir & mask2) { in handle_data_dl()
1041 writew(mask2, dc->reg_fcr); in handle_data_dl()
1045 } else if (*toggle == 1 && read_iir & mask2) { in handle_data_dl()
1047 writew(mask2, dc->reg_fcr); in handle_data_dl()
/drivers/usb/host/
Dr8a66597-hcd.c1607 u16 mask0, mask1, mask2; in r8a66597_irq() local
1619 mask2 = intsts2 & intenb2; in r8a66597_irq()
1622 if (mask2) { in r8a66597_irq()
1623 if (mask2 & ATTCH) { in r8a66597_irq()
1630 if (mask2 & DTCH) { in r8a66597_irq()
1635 if (mask2 & BCHG) { in r8a66597_irq()
/drivers/edac/
Dthunderx_edac.c191 u64 mask2; member
352 writeq(lmc->mask2, lmc->regs + LMC_CHAR_MASK2); in inject_ecc_fn()
450 LMC_DEBUGFS_ENT(mask2);
/drivers/media/pci/bt8xx/
Dbttv-driver.c938 int mux,mask2; in video_mux() local
944 mask2 = bttv_tvcards[btv->c.type].gpiomask2; in video_mux()
945 if (mask2) in video_mux()
946 gpio_inout(mask2,mask2); in video_mux()
/drivers/infiniband/hw/hfi1/
Dchip.c14107 u32 mask2; member
14168 (u64)rrd->mask2 << RCV_RSM_MATCH_MASK2_SHIFT | in add_rsm_rule()
14293 rrd.mask2 = LRH_SC_MASK; in init_qos()
14375 rrd.mask2 = 1; in init_fecn_handling()
14435 rrd.mask2 = L4_16B_TYPE_MASK; in hfi1_init_vnic_rsm()