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Searched refs:misses (Results 1 – 5 of 5) sorted by relevance

/drivers/cpuidle/governors/
Dteo.c91 unsigned int misses; member
175 unsigned int misses = cpu_data->states[idx_timer].misses; in teo_update() local
178 misses -= misses >> DECAY_SHIFT; in teo_update()
181 misses += PULSE; in teo_update()
188 cpu_data->states[idx_timer].misses = misses; in teo_update()
236 unsigned int duration_us, hits, misses, early_hits; in teo_select() local
251 misses = 0; in teo_select()
278 misses = cpu_data->states[i].misses; in teo_select()
316 misses = cpu_data->states[i].misses; in teo_select()
327 misses = cpu_data->states[i].misses; in teo_select()
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/drivers/video/fbdev/riva/
Driva_hw.c249 int misses; in nv3_iterate() local
334 if (last==cur) misses = 0; in nv3_iterate()
335 else if (ainfo->first_vacc) misses = vmisses; in nv3_iterate()
336 else misses = 1; in nv3_iterate()
344 …ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mcl… in nv3_iterate()
350 if (last==cur) misses = 0; in nv3_iterate()
351 else if (ainfo->first_gacc) misses = gmisses; in nv3_iterate()
352 else misses = 1; in nv3_iterate()
360 …ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mcl… in nv3_iterate()
366 if (last==cur) misses = 0; in nv3_iterate()
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/drivers/md/
Ddm-cache-policy-smq.c517 unsigned misses; member
530 s->misses = 0u; in stats_init()
535 s->hits = s->misses = 0u; in stats_reset()
543 s->misses++; in stats_level_accessed()
548 s->misses++; in stats_miss()
559 unsigned confidence = safe_div(s->hits << FP_SHIFT, s->hits + s->misses); in stats_assess()
1032 unsigned misses = mq->cache_stats.misses; in default_promote_level() local
1033 unsigned index = safe_div(hits << 4u, hits + misses); in default_promote_level()
/drivers/net/ethernet/myricom/
DKconfig43 is used, with the intent of lessening the impact of cache misses.
/drivers/net/ethernet/intel/
DKconfig124 is used, with the intent of lessening the impact of cache misses.
193 is used, with the intent of lessening the impact of cache misses.