| /drivers/media/pci/solo6x10/ |
| D | solo6x10-regs.h | 34 #define SOLO_DMA_CTRL_REFRESH_CYCLE(n) ((n)<<8) argument
36 #define SOLO_DMA_CTRL_SDRAM_SIZE(n) ((n)<<6) argument
41 #define SOLO_DMA_CTRL_LATENCY(n) ((n)<<0) argument
49 #define SOLO_VCLK_SELECT(n) ((n)<<20) argument
50 #define SOLO_VCLK_VIN1415_DELAY(n) ((n)<<14) argument
51 #define SOLO_VCLK_VIN1213_DELAY(n) ((n)<<12) argument
52 #define SOLO_VCLK_VIN1011_DELAY(n) ((n)<<10) argument
53 #define SOLO_VCLK_VIN0809_DELAY(n) ((n)<<8) argument
54 #define SOLO_VCLK_VIN0607_DELAY(n) ((n)<<6) argument
55 #define SOLO_VCLK_VIN0405_DELAY(n) ((n)<<4) argument
[all …]
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| D | solo6x10-tw28.h | 19 #define TW_CHIP_OFFSET_ADDR(n) (TW_BASE_ADDR + (n)) argument
23 #define TW_HUE_ADDR(n) (0x07 | ((n) << 4)) argument
24 #define TW_SATURATION_ADDR(n) (0x08 | ((n) << 4)) argument
25 #define TW_CONTRAST_ADDR(n) (0x09 | ((n) << 4)) argument
26 #define TW_BRIGHTNESS_ADDR(n) (0x0a | ((n) << 4)) argument
28 #define TW_AUDIO_INPUT_GAIN_ADDR(n) (0x60 + ((n > 1) ? 1 : 0)) argument
32 #define TW286x_HUE_ADDR(n) (0x06 | ((n) << 4)) argument
33 #define TW286x_SATURATIONU_ADDR(n) (0x04 | ((n) << 4)) argument
34 #define TW286x_SATURATIONV_ADDR(n) (0x05 | ((n) << 4)) argument
35 #define TW286x_CONTRAST_ADDR(n) (0x02 | ((n) << 4)) argument
[all …]
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| /drivers/media/common/siano/ |
| D | smsdvb-debugfs.c | 37 int n = 0; in smsdvb_print_dvb_stats() local
48 n += snprintf(&buf[n], PAGE_SIZE - n, in smsdvb_print_dvb_stats()
50 n += snprintf(&buf[n], PAGE_SIZE - n, in smsdvb_print_dvb_stats()
52 n += snprintf(&buf[n], PAGE_SIZE - n, in smsdvb_print_dvb_stats()
54 n += snprintf(&buf[n], PAGE_SIZE - n, in smsdvb_print_dvb_stats()
56 n += snprintf(&buf[n], PAGE_SIZE - n, in smsdvb_print_dvb_stats()
58 n += snprintf(&buf[n], PAGE_SIZE - n, in smsdvb_print_dvb_stats()
60 n += snprintf(&buf[n], PAGE_SIZE - n, in smsdvb_print_dvb_stats()
62 n += snprintf(&buf[n], PAGE_SIZE - n, in smsdvb_print_dvb_stats()
64 n += snprintf(&buf[n], PAGE_SIZE - n, in smsdvb_print_dvb_stats()
[all …]
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| /drivers/media/cec/ |
| D | cec-notifier.c | 39 struct cec_notifier *n; in cec_notifier_get_conn() local
42 list_for_each_entry(n, &cec_notifiers, head) { in cec_notifier_get_conn()
43 if (n->hdmi_dev == hdmi_dev && in cec_notifier_get_conn()
45 (n->conn_name && !strcmp(n->conn_name, conn_name)))) { in cec_notifier_get_conn()
46 kref_get(&n->kref); in cec_notifier_get_conn()
48 return n; in cec_notifier_get_conn()
51 n = kzalloc(sizeof(*n), GFP_KERNEL); in cec_notifier_get_conn()
52 if (!n) in cec_notifier_get_conn()
54 n->hdmi_dev = hdmi_dev; in cec_notifier_get_conn()
56 n->conn_name = kstrdup(conn_name, GFP_KERNEL); in cec_notifier_get_conn()
[all …]
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| /drivers/gpu/drm/rockchip/ |
| D | inno_hdmi.h | 48 #define v_VIDEO_INPUT_FORMAT(n) (n << 1) argument
61 #define v_VIDEO_OUTPUT_COLOR(n) (((n) & 0x3) << 6) argument
62 #define v_VIDEO_INPUT_BITS(n) (n << 4) argument
63 #define v_VIDEO_INPUT_CSP(n) (n << 0) argument
73 #define v_VIDEO_AUTO_CSC(n) (n << 7) argument
75 #define v_VIDEO_C0_C2_SWAP(n) (n << 0) argument
88 #define v_COLOR_DEPTH_NOT_INDICATED(n) ((n) << 4) argument
101 #define v_AVMUTE_CLEAR(n) (n << 7) argument
102 #define v_AVMUTE_ENABLE(n) (n << 6) argument
103 #define v_AUDIO_MUTE(n) (n << 1) argument
[all …]
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| /drivers/gpu/drm/exynos/ |
| D | regs-decon5433.h | 12 #define DECON_WINCONx(n) (0x0020 + ((n) * 4)) argument
13 #define DECON_VIDOSDxH(n) (0x0080 + ((n) * 4)) argument
15 #define DECON_VIDOSDxA(n) (0x00B0 + ((n) * 0x20)) argument
16 #define DECON_VIDOSDxB(n) (0x00B4 + ((n) * 0x20)) argument
17 #define DECON_VIDOSDxC(n) (0x00B8 + ((n) * 0x20)) argument
18 #define DECON_VIDOSDxD(n) (0x00BC + ((n) * 0x20)) argument
19 #define DECON_VIDOSDxE(n) (0x00C0 + ((n) * 0x20)) argument
20 #define DECON_VIDW0xADD0B0(n) (0x0150 + ((n) * 0x10)) argument
21 #define DECON_VIDW0xADD0B1(n) (0x0154 + ((n) * 0x10)) argument
22 #define DECON_VIDW0xADD0B2(n) (0x0158 + ((n) * 0x10)) argument
[all …]
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| /drivers/usb/gadget/udc/ |
| D | fusb300_udc.h | 21 #define FUSB300_OFFSET_EPSET0(n) (0x20 + (n - 1) * 0x30) argument
22 #define FUSB300_OFFSET_EPSET1(n) (0x24 + (n - 1) * 0x30) argument
23 #define FUSB300_OFFSET_EPSET2(n) (0x28 + (n - 1) * 0x30) argument
24 #define FUSB300_OFFSET_EPFFR(n) (0x2c + (n - 1) * 0x30) argument
25 #define FUSB300_OFFSET_EPSTRID(n) (0x40 + (n - 1) * 0x30) argument
54 #define FUSB300_OFFSET_EPPRD_W0(n) (0x520 + (n - 1) * 0x10) argument
55 #define FUSB300_OFFSET_EPPRD_W1(n) (0x524 + (n - 1) * 0x10) argument
56 #define FUSB300_OFFSET_EPPRD_W2(n) (0x528 + (n - 1) * 0x10) argument
57 #define FUSB300_OFFSET_EPRD_PTR(n) (0x52C + (n - 1) * 0x10) argument
60 #define FUSB300_OFFSET_EPPORT(n) (0x1010 + (n - 1) * 0x10) argument
[all …]
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| /drivers/clk/at91/ |
| D | sam9x60.c | 60 char *n; member
64 { .n = "ddrck", .p = "masterck", .id = 2 },
65 { .n = "uhpck", .p = "usbck", .id = 6 },
66 { .n = "pck0", .p = "prog0", .id = 8 },
67 { .n = "pck1", .p = "prog1", .id = 9 },
68 { .n = "qspick", .p = "masterck", .id = 19 },
72 char *n; member
75 { .n = "pioA_clk", .id = 2, },
76 { .n = "pioB_clk", .id = 3, },
77 { .n = "pioC_clk", .id = 4, },
[all …]
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| D | sama5d4.c | 38 char *n; member
42 { .n = "ddrck", .p = "masterck", .id = 2 },
43 { .n = "lcdck", .p = "masterck", .id = 3 },
44 { .n = "smdck", .p = "smdclk", .id = 4 },
45 { .n = "uhpck", .p = "usbck", .id = 6 },
46 { .n = "udpck", .p = "usbck", .id = 7 },
47 { .n = "pck0", .p = "prog0", .id = 8 },
48 { .n = "pck1", .p = "prog1", .id = 9 },
49 { .n = "pck2", .p = "prog2", .id = 10 },
53 char *n; member
[all …]
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| D | at91sam9260.c | 11 char *n; member
17 char *n; member
74 { .n = "uhpck", .p = "usbck", .id = 6 },
75 { .n = "udpck", .p = "usbck", .id = 7 },
76 { .n = "pck0", .p = "prog0", .id = 8 },
77 { .n = "pck1", .p = "prog1", .id = 9 },
81 { .n = "pioA_clk", .id = 2 },
82 { .n = "pioB_clk", .id = 3 },
83 { .n = "pioC_clk", .id = 4 },
84 { .n = "adc_clk", .id = 5 },
[all …]
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| D | sama5d2.c | 39 char *n; member
43 { .n = "ddrck", .p = "masterck", .id = 2 },
44 { .n = "lcdck", .p = "masterck", .id = 3 },
45 { .n = "uhpck", .p = "usbck", .id = 6 },
46 { .n = "udpck", .p = "usbck", .id = 7 },
47 { .n = "pck0", .p = "prog0", .id = 8 },
48 { .n = "pck1", .p = "prog1", .id = 9 },
49 { .n = "pck2", .p = "prog2", .id = 10 },
50 { .n = "iscck", .p = "masterck", .id = 18 },
54 char *n; member
[all …]
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| D | at91sam9x5.c | 40 char *n; member
44 { .n = "ddrck", .p = "masterck", .id = 2 },
45 { .n = "smdck", .p = "smdclk", .id = 4 },
46 { .n = "uhpck", .p = "usbck", .id = 6 },
47 { .n = "udpck", .p = "usbck", .id = 7 },
48 { .n = "pck0", .p = "prog0", .id = 8 },
49 { .n = "pck1", .p = "prog1", .id = 9 },
60 char *n; member
65 { .n = "pioAB_clk", .id = 2, },
66 { .n = "pioCD_clk", .id = 3, },
[all …]
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| /drivers/usb/dwc3/ |
| D | core.h | 123 #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04)) argument
124 #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04)) argument
126 #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04)) argument
128 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04)) argument
130 #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04)) argument
131 #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04)) argument
133 #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10)) argument
134 #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10)) argument
135 #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10)) argument
136 #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) argument
[all …]
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| /drivers/media/platform/vsp1/ |
| D | vsp1_regs.h | 17 #define VI6_CMD(n) (0x0000 + (n) * 4) argument
28 #define VI6_SRESET_SRTS(n) BIT(n) argument
31 #define VI6_STATUS_FLD_STD(n) BIT((n) + 28) argument
32 #define VI6_STATUS_SYS_ACT(n) BIT((n) + 8) argument
34 #define VI6_WPF_IRQ_ENB(n) (0x0048 + (n) * 12) argument
38 #define VI6_WPF_IRQ_STA(n) (0x004c + (n) * 12) argument
42 #define VI6_DISP_IRQ_ENB(n) (0x0078 + (n) * 60) argument
45 #define VI6_DISP_IRQ_ENB_LNEE(n) BIT(n) argument
47 #define VI6_DISP_IRQ_STA(n) (0x007c + (n) * 60) argument
50 #define VI6_DISP_IRQ_STA_LNE(n) BIT(n) argument
[all …]
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| /drivers/video/fbdev/omap2/omapfb/dss/ |
| D | dispc.h | 34 #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \ argument
35 DISPC_BA0_OFFSET(n))
36 #define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \ argument
37 DISPC_BA1_OFFSET(n))
38 #define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \ argument
39 DISPC_BA0_UV_OFFSET(n))
40 #define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \ argument
41 DISPC_BA1_UV_OFFSET(n))
42 #define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \ argument
43 DISPC_POS_OFFSET(n))
[all …]
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| /drivers/gpu/drm/omapdrm/dss/ |
| D | dispc.h | 37 #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \ argument
38 DISPC_BA0_OFFSET(n))
39 #define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \ argument
40 DISPC_BA1_OFFSET(n))
41 #define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \ argument
42 DISPC_BA0_UV_OFFSET(n))
43 #define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \ argument
44 DISPC_BA1_UV_OFFSET(n))
45 #define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \ argument
46 DISPC_POS_OFFSET(n))
[all …]
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| /drivers/gpu/drm/rcar-du/ |
| D | rcar_du_regs.h | 72 #define DSSR_DFB(n) (1 << ((n)+15)) argument
78 #define DSSR_ADC(n) (1 << ((n)-1)) argument
86 #define DSRCR_ADCL(n) (1 << ((n)-1)) argument
95 #define DIER_ADCE(n) (1 << ((n)-1)) argument
104 #define DPPR_DPE(n) (1 << ((n)*4-1)) argument
105 #define DPPR_DPS(n, p) (((p)-1) << DPPR_DPS_SHIFT(n)) argument
106 #define DPPR_DPS_SHIFT(n) (((n)-1)*4) argument
154 #define DVCSR_VCnFB2_DSA0(n) (0 << ((n)*2+16)) argument
155 #define DVCSR_VCnFB2_DSA1(n) (1 << ((n)*2+16)) argument
156 #define DVCSR_VCnFB2_DSA2(n) (2 << ((n)*2+16)) argument
[all …]
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| /drivers/gpu/drm/panel/ |
| D | panel-sitronix-st7789v.c | 26 #define ST7789V_RAMCTRL_EPF(n) (((n) & 3) << 4) argument
30 #define ST7789V_RGBCTRL_RCM(n) (((n) & 3) << 5) argument
34 #define ST7789V_RGBCTRL_VBP(n) ((n) & 0x7f) argument
35 #define ST7789V_RGBCTRL_HBP(n) ((n) & 0x1f) argument
38 #define ST7789V_PORCTRL_IDLE_BP(n) (((n) & 0xf) << 4) argument
39 #define ST7789V_PORCTRL_IDLE_FP(n) ((n) & 0xf) argument
40 #define ST7789V_PORCTRL_PARTIAL_BP(n) (((n) & 0xf) << 4) argument
41 #define ST7789V_PORCTRL_PARTIAL_FP(n) ((n) & 0xf) argument
44 #define ST7789V_GCTRL_VGHS(n) (((n) & 7) << 4) argument
45 #define ST7789V_GCTRL_VGLS(n) ((n) & 7) argument
[all …]
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| /drivers/vhost/ |
| D | test.c | 43 static void handle_vq(struct vhost_test *n) in handle_vq() argument
45 struct vhost_virtqueue *vq = &n->vqs[VHOST_TEST_VQ]; in handle_vq()
58 vhost_disable_notify(&n->dev, vq); in handle_vq()
70 if (unlikely(vhost_enable_notify(&n->dev, vq))) { in handle_vq()
71 vhost_disable_notify(&n->dev, vq); in handle_vq()
87 vhost_add_used_and_signal(&n->dev, vq, head, 0); in handle_vq()
100 struct vhost_test *n = container_of(vq->dev, struct vhost_test, dev); in handle_vq_kick() local
102 handle_vq(n); in handle_vq_kick()
107 struct vhost_test *n = kmalloc(sizeof *n, GFP_KERNEL); in vhost_test_open() local
111 if (!n) in vhost_test_open()
[all …]
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| /drivers/crypto/inside-secure/ |
| D | safexcel.h | 128 #define EIP197_HIA_DFE_CFG(n) (0x0000 + (128 * (n))) argument
129 #define EIP197_HIA_DFE_THR_CTRL(n) (0x0000 + (128 * (n))) argument
130 #define EIP197_HIA_DFE_THR_STAT(n) (0x0004 + (128 * (n))) argument
131 #define EIP197_HIA_DSE_CFG(n) (0x0000 + (128 * (n))) argument
132 #define EIP197_HIA_DSE_THR_CTRL(n) (0x0000 + (128 * (n))) argument
133 #define EIP197_HIA_DSE_THR_STAT(n) (0x0004 + (128 * (n))) argument
134 #define EIP197_HIA_RA_PE_CTRL(n) (0x0010 + (8 * (n))) argument
147 #define EIP197_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n))) argument
148 #define EIP197_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n))) argument
149 #define EIP197_PE_ICE_SCRATCH_RAM(n) (0x0800 + (0x2000 * (n))) argument
[all …]
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| /drivers/gpu/drm/selftests/ |
| D | test-drm_mm.c | 109 unsigned long n; in assert_continuous() local
115 n = 0; in assert_continuous()
120 n, addr, node->start); in assert_continuous()
126 n, size, node->size); in assert_continuous()
131 pr_err("node[%ld] is followed by a hole!\n", n); in assert_continuous()
151 n++; in assert_continuous()
355 int n; in check_reserve_boundaries() local
357 for (n = 0; n < ARRAY_SIZE(boundaries); n++) { in check_reserve_boundaries()
360 boundaries[n].start, in check_reserve_boundaries()
361 boundaries[n].size))) { in check_reserve_boundaries()
[all …]
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| /drivers/phy/allwinner/ |
| D | phy-sun6i-mipi-dphy.c | 21 #define SUN6I_DPHY_GCTL_LANE_NUM(n) ((((n) - 1) & 3) << 4) argument
28 #define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n) (((n) & 0xff) << 24) argument
29 #define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n) (((n) & 0xff) << 16) argument
30 #define SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(n) ((n) & 0xff) argument
33 #define SUN6I_DPHY_TX_TIME1_CLK_POST(n) (((n) & 0xff) << 24) argument
34 #define SUN6I_DPHY_TX_TIME1_CLK_PRE(n) (((n) & 0xff) << 16) argument
35 #define SUN6I_DPHY_TX_TIME1_CLK_ZERO(n) (((n) & 0xff) << 8) argument
36 #define SUN6I_DPHY_TX_TIME1_CLK_PREPARE(n) ((n) & 0xff) argument
39 #define SUN6I_DPHY_TX_TIME2_CLK_TRAIL(n) ((n) & 0xff) argument
44 #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n) (((n) & 0xff) << 8) argument
[all …]
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| /drivers/video/fbdev/ |
| D | c2p_core.h | 32 static __always_inline u32 get_mask(unsigned int n) in get_mask() argument
34 switch (n) { in get_mask()
60 static __always_inline void transp8(u32 d[], unsigned int n, unsigned int m) in transp8() argument
62 u32 mask = get_mask(n); in transp8()
67 _transp(d, 0, 1, n, mask); in transp8()
69 _transp(d, 2, 3, n, mask); in transp8()
71 _transp(d, 4, 5, n, mask); in transp8()
73 _transp(d, 6, 7, n, mask); in transp8()
78 _transp(d, 0, 2, n, mask); in transp8()
79 _transp(d, 1, 3, n, mask); in transp8()
[all …]
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| /drivers/net/ethernet/freescale/enetc/ |
| D | enetc_hw.h | 50 #define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */ argument
51 #define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */ argument
52 #define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8) argument
72 #define ENETC_RBDCR(n) (0x8180 + (n) * 0x200) argument
93 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4) argument
94 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4) argument
145 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7) argument
153 #define ENETC_PSIPMR_SET_UP(n) BIT(n) /* n = SI index */ argument
154 #define ENETC_PSIPMR_SET_MP(n) BIT((n) + 16) argument
159 #define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */ argument
[all …]
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| /drivers/gpu/drm/panfrost/ |
| D | panfrost_regs.h | 79 #define GPU_TEXTURE_FEATURES(n) (0x0B0 + ((n) * 4)) argument
80 #define GPU_JS_FEATURES(n) (0x0C0 + ((n) * 4)) argument
222 #define JS_HEAD_LO(n) (JS_BASE + ((n) * 0x80) + 0x00) argument
223 #define JS_HEAD_HI(n) (JS_BASE + ((n) * 0x80) + 0x04) argument
224 #define JS_TAIL_LO(n) (JS_BASE + ((n) * 0x80) + 0x08) argument
225 #define JS_TAIL_HI(n) (JS_BASE + ((n) * 0x80) + 0x0c) argument
226 #define JS_AFFINITY_LO(n) (JS_BASE + ((n) * 0x80) + 0x10) argument
227 #define JS_AFFINITY_HI(n) (JS_BASE + ((n) * 0x80) + 0x14) argument
228 #define JS_CONFIG(n) (JS_BASE + ((n) * 0x80) + 0x18) argument
229 #define JS_XAFFINITY(n) (JS_BASE + ((n) * 0x80) + 0x1c) argument
[all …]
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