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Searched refs:num_heads (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/qxl/
Dqxl_drv.c60 MODULE_PARM_DESC(num_heads, "Number of virtual crtcs to expose (default 4)");
61 module_param_named(num_heads, qxl_num_crtc, int, 0400);
/drivers/gpu/drm/amd/amdgpu/
Ddce_v8_0.c634 u32 num_heads; /* number of active crtcs */ member
827 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v8_0_latency_watermark()
828 (wm->num_heads * cursor_line_pair_return_time); in dce_v8_0_latency_watermark()
834 if (wm->num_heads == 0) in dce_v8_0_latency_watermark()
848 b.full = dfixed_const(wm->num_heads); in dce_v8_0_latency_watermark()
883 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display()
903 (dce_v8_0_available_bandwidth(wm) / wm->num_heads)) in dce_v8_0_average_bandwidth_vs_available_bandwidth()
957 u32 lb_size, u32 num_heads) in dce_v8_0_program_watermarks() argument
966 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v8_0_program_watermarks()
998 wm_high.num_heads = num_heads; in dce_v8_0_program_watermarks()
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Ddce_v6_0.c498 u32 num_heads; /* number of active crtcs */ member
691 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v6_0_latency_watermark()
692 (wm->num_heads * cursor_line_pair_return_time); in dce_v6_0_latency_watermark()
698 if (wm->num_heads == 0) in dce_v6_0_latency_watermark()
712 b.full = dfixed_const(wm->num_heads); in dce_v6_0_latency_watermark()
747 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display()
767 (dce_v6_0_available_bandwidth(wm) / wm->num_heads)) in dce_v6_0_average_bandwidth_vs_available_bandwidth()
821 u32 lb_size, u32 num_heads) in dce_v6_0_program_watermarks() argument
835 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v6_0_program_watermarks()
871 wm_high.num_heads = num_heads; in dce_v6_0_program_watermarks()
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Ddce_v11_0.c725 u32 num_heads; /* number of active crtcs */ member
918 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v11_0_latency_watermark()
919 (wm->num_heads * cursor_line_pair_return_time); in dce_v11_0_latency_watermark()
925 if (wm->num_heads == 0) in dce_v11_0_latency_watermark()
939 b.full = dfixed_const(wm->num_heads); in dce_v11_0_latency_watermark()
974 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display()
994 (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) in dce_v11_0_average_bandwidth_vs_available_bandwidth()
1048 u32 lb_size, u32 num_heads) in dce_v11_0_program_watermarks() argument
1057 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v11_0_program_watermarks()
1089 wm_high.num_heads = num_heads; in dce_v11_0_program_watermarks()
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Ddce_v10_0.c699 u32 num_heads; /* number of active crtcs */ member
892 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v10_0_latency_watermark()
893 (wm->num_heads * cursor_line_pair_return_time); in dce_v10_0_latency_watermark()
899 if (wm->num_heads == 0) in dce_v10_0_latency_watermark()
913 b.full = dfixed_const(wm->num_heads); in dce_v10_0_latency_watermark()
948 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display()
968 (dce_v10_0_available_bandwidth(wm) / wm->num_heads)) in dce_v10_0_average_bandwidth_vs_available_bandwidth()
1022 u32 lb_size, u32 num_heads) in dce_v10_0_program_watermarks() argument
1031 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v10_0_program_watermarks()
1063 wm_high.num_heads = num_heads; in dce_v10_0_program_watermarks()
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/drivers/gpu/drm/tegra/
Dhub.c806 hub->num_heads = of_get_child_count(pdev->dev.of_node); in tegra_display_hub_probe()
808 hub->clk_heads = devm_kcalloc(&pdev->dev, hub->num_heads, sizeof(clk), in tegra_display_hub_probe()
813 for (i = 0; i < hub->num_heads; i++) { in tegra_display_hub_probe()
873 unsigned int i = hub->num_heads; in tegra_display_hub_suspend()
908 for (i = 0; i < hub->num_heads; i++) { in tegra_display_hub_resume()
Dhub.h48 unsigned int num_heads; member
/drivers/gpu/drm/radeon/
Devergreen.c1941 u32 num_heads; /* number of active crtcs */ member
2069 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in evergreen_latency_watermark()
2070 (wm->num_heads * cursor_line_pair_return_time); in evergreen_latency_watermark()
2075 if (wm->num_heads == 0) in evergreen_latency_watermark()
2089 b.full = dfixed_const(wm->num_heads); in evergreen_latency_watermark()
2111 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads)) in evergreen_average_bandwidth_vs_dram_bandwidth_for_display()
2120 (evergreen_available_bandwidth(wm) / wm->num_heads)) in evergreen_average_bandwidth_vs_available_bandwidth()
2154 u32 lb_size, u32 num_heads) in evergreen_program_watermarks() argument
2169 if (radeon_crtc->base.enabled && num_heads && mode) { in evergreen_program_watermarks()
2204 wm_high.num_heads = num_heads; in evergreen_program_watermarks()
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Dsi.c2067 u32 num_heads; /* number of active crtcs */ member
2212 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce6_latency_watermark()
2213 (wm->num_heads * cursor_line_pair_return_time); in dce6_latency_watermark()
2219 if (wm->num_heads == 0) in dce6_latency_watermark()
2233 b.full = dfixed_const(wm->num_heads); in dce6_latency_watermark()
2257 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce6_average_bandwidth_vs_dram_bandwidth_for_display()
2266 (dce6_available_bandwidth(wm) / wm->num_heads)) in dce6_average_bandwidth_vs_available_bandwidth()
2300 u32 lb_size, u32 num_heads) in dce6_program_watermarks() argument
2314 if (radeon_crtc->base.enabled && num_heads && mode) { in dce6_program_watermarks()
2353 wm_high.num_heads = num_heads; in dce6_program_watermarks()
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Dcik.c8929 u32 num_heads; /* number of active crtcs */ member
9122 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce8_latency_watermark()
9123 (wm->num_heads * cursor_line_pair_return_time); in dce8_latency_watermark()
9129 if (wm->num_heads == 0) in dce8_latency_watermark()
9143 b.full = dfixed_const(wm->num_heads); in dce8_latency_watermark()
9178 (dce8_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce8_average_bandwidth_vs_dram_bandwidth_for_display()
9198 (dce8_available_bandwidth(wm) / wm->num_heads)) in dce8_average_bandwidth_vs_available_bandwidth()
9252 u32 lb_size, u32 num_heads) in dce8_program_watermarks() argument
9261 if (radeon_crtc->base.enabled && num_heads && mode) { in dce8_program_watermarks()
9294 wm_high.num_heads = num_heads; in dce8_program_watermarks()
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/drivers/staging/exfat/
Dexfat.h335 u8 num_heads[2]; member
358 u8 num_heads[2]; member