| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_mpc.c | 130 unsigned int opp_id; in mpc1_is_mpcc_idle() local
134 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_is_mpcc_idle()
136 if (top_sel == 0xf && opp_id == 0xf && idle) in mpc1_is_mpcc_idle()
217 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); in mpc1_insert_plane()
223 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id); in mpc1_insert_plane()
279 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id); in mpc1_remove_mpcc()
283 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf); in mpc1_remove_mpcc()
350 int opp_id; in mpc1_mpc_init() local
361 for (opp_id = 0; opp_id < MAX_OPP; opp_id++) { in mpc1_mpc_init()
362 if (REG(MUX[opp_id])) in mpc1_mpc_init()
[all …]
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| D | dcn10_hw_sequencer.c | 303 if (s.opp_id != 0xf) in dcn10_log_hw_state()
305 i, s.opp_id, s.dpp_id, s.bot_mpcc_id, in dcn10_log_hw_state()
1033 int opp_id = hubp->opp_id; in dcn10_plane_atomic_disable() local
1041 if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL) in dcn10_plane_atomic_disable()
1153 hubp->opp_id = OPP_ID_INVALID; in dcn10_init_pipes()
1156 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; in dcn10_init_pipes()
1946 int opp_id) in dcn10_program_output_csc() argument
2263 hubp->opp_id = pipe_ctx->stream_res.opp->inst; in dcn10_update_mpcc()
2608 old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID) in dcn10_apply_ctx_for_surface()
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| D | dcn10_hw_sequencer_debug.c | 399 if (s.opp_id != 0xf) { in dcn10_get_mpcc_states()
401 i, s.opp_id, s.dpp_id, s.bot_mpcc_id, in dcn10_get_mpcc_states()
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| D | dcn10_hubp.c | 66 hubp->opp_id = OPP_ID_INVALID; in hubp1_set_blank()
1267 hubp1->base.opp_id = OPP_ID_INVALID; in dcn10_hubp_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_mpc.c | 73 int opp_id, in mpc2_set_denorm() argument
105 REG_UPDATE(DENORM_CONTROL[opp_id], in mpc2_set_denorm()
111 int opp_id, in mpc2_set_denorm_clamp() argument
116 REG_UPDATE_2(DENORM_CONTROL[opp_id], in mpc2_set_denorm_clamp()
119 REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id], in mpc2_set_denorm_clamp()
122 REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id], in mpc2_set_denorm_clamp()
131 int opp_id, in mpc2_set_output_csc() argument
138 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
154 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); in mpc2_set_output_csc()
155 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); in mpc2_set_output_csc()
[all …]
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| D | dcn20_mpc.h | 261 int opp_id,
266 int opp_id,
271 int opp_id,
277 int opp_id,
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| D | dcn20_optc.c | 232 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc2_set_odm_combine() argument
263 OPTC_SEG0_SRC_SEL, opp_id[0], in optc2_set_odm_combine()
264 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc2_set_odm_combine()
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| D | dcn20_hwseq.h | 47 int opp_id);
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| D | dcn20_optc.h | 99 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
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| D | dcn20_hwseq.c | 628 int opp_id) in dcn20_program_output_csc() argument
640 opp_id, in dcn20_program_output_csc()
646 opp_id, in dcn20_program_output_csc()
1207 old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID) in dcn20_apply_ctx_for_surface()
1800 hubp->opp_id = pipe_ctx->stream_res.opp->inst; in dcn20_update_mpcc()
2049 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; in dcn20_fpga_init_hw()
2068 hubp->opp_id = OPP_ID_INVALID; in dcn20_fpga_init_hw()
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| D | dcn20_hubp.c | 934 hubp->opp_id = OPP_ID_INVALID; in hubp2_set_blank()
1286 hubp2->base.opp_id = OPP_ID_INVALID; in hubp2_construct()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | mpc.h | 120 int opp_id; /* The OPP instance that owns this MPC tree */ member
136 uint32_t opp_id; member
235 int opp_id,
240 int opp_id,
244 int opp_id,
249 int opp_id,
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| D | hubp.h | 62 int opp_id; member
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| D | timing_generator.h | 276 void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_hubp.c | 240 hubp21->base.opp_id = OPP_ID_INVALID; in hubp21_construct()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | hw_sequencer.h | 114 int opp_id);
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_hw_sequencer.c | 2665 int opp_id) in program_output_csc() argument
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