| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer_debug.c | 133 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_hubp_states()
203 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_rq_states()
248 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_dlg_states()
302 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_ttu_states()
341 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_cm_states()
394 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_mpcc_states()
509 for (i = 0; i < pool->pipe_count; i++) { in dcn10_clear_hubp_underflow()
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| D | dcn10_hw_sequencer.c | 135 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
167 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
192 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
224 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
257 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
299 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
649 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_DEGVIDCN10_253_wa()
689 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_bios_golden_init()
715 for (i = 0; i < dc->res_pool->pipe_count; i++) { in false_optc_underflow_wa()
863 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn10_reset_back_end_for_pipe()
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| D | dcn10_resource.c | 906 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
1300 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in construct()
1303 pool->base.pipe_count = 3; in construct()
1447 for (i = 0; i < pool->base.pipe_count; i++) { in construct()
1516 pool->base.pipe_count = j; in construct()
1522 dc->dml.ip.max_num_dpp = pool->base.pipe_count; in construct()
1523 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in construct()
1545 dc->caps.max_planes = pool->base.pipe_count; in construct()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc.c | 752 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_dangling_plane()
795 full_pipe_count = dc->res_pool->pipe_count; in dc_create()
844 int pipe_count = dc->res_pool->pipe_count; in enable_timing_multisync() local
847 for (i = 0; i < pipe_count; i++) { in enable_timing_multisync()
870 int pipe_count = dc->res_pool->pipe_count; in program_timing_sync() local
873 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
880 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
893 for (j = i + 1; j < pipe_count; j++) { in program_timing_sync()
989 if (enc_inst >= dc->res_pool->pipe_count) in dc_validate_seamless_boot_timing()
1091 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_commit_state_no_check()
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| D | dc_surface.c | 161 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
173 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
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| D | dc_debug.c | 320 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { in context_timing_trace()
332 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { in context_timing_trace()
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| D | dc_resource.c | 1105 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; in find_idle_secondary_pipe()
1117 for (i = pool->pipe_count - 1; i >= 0; i--) { in find_idle_secondary_pipe()
1175 for (i = pool->pipe_count - 1; i >= 0; i--) { in acquire_free_pipe_for_head()
1201 for (i = 0; i < pool->pipe_count; i++) { in acquire_first_split_pipe()
1330 for (i = pool->pipe_count - 1; i >= 0; i--) { in dc_remove_plane_from_context()
1612 for (i = 0; i < pool->pipe_count; i++) { in acquire_first_free_pipe()
1872 if (inst >= pool->pipe_count) in acquire_resource_from_hw_enabled_state()
2054 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dc_validate_global_state()
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_resource.c | 743 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
906 dc->res_pool->pipe_count, in dce110_validate_bandwidth()
1192 pool->opps[pool->pipe_count] = &dce110_oppv->base; in underlay_create()
1193 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; in underlay_create()
1194 pool->mis[pool->pipe_count] = &dce110_miv->base; in underlay_create()
1195 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; in underlay_create()
1196 pool->pipe_count++; in underlay_create()
1289 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in construct()
1290 pool->base.underlay_pipe_index = pool->base.pipe_count; in construct()
1361 for (i = 0; i < pool->base.pipe_count; i++) { in construct()
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| D | dce110_hw_sequencer.c | 1508 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vga_and_power_gate_all_controllers()
1810 for (i = 0; i < dc->res_pool->pipe_count; i++) { in should_enable_fbc()
1826 if (i == dc->res_pool->pipe_count) in should_enable_fbc()
1973 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_setup_audio_dto()
2000 if (i == dc->res_pool->pipe_count) { in dce110_setup_audio_dto()
2001 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_setup_audio_dto()
2049 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_apply_ctx_to_hw()
2074 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_apply_ctx_to_hw()
2375 for (i = 0; i < dc->res_pool->pipe_count; i++) { in init_hw()
2403 for (i = 0; i < dc->res_pool->pipe_count; i++) { in init_hw()
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| /drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_resource.c | 734 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
807 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce80_validate_bandwidth()
892 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
970 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_construct()
1032 dc->caps.max_planes = pool->base.pipe_count; in dce80_construct()
1089 pool->base.pipe_count = res_cap_81.num_timing_generator; in dce81_construct()
1167 for (i = 0; i < pool->base.pipe_count; i++) { in dce81_construct()
1229 dc->caps.max_planes = pool->base.pipe_count; in dce81_construct()
1286 pool->base.pipe_count = res_cap_83.num_timing_generator; in dce83_construct()
1360 for (i = 0; i < pool->base.pipe_count; i++) { in dce83_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 1219 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
1472 for (i = 0; i < dc->res_pool->pipe_count; i++) { in add_dsc_to_stream_resource()
1729 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_writeback_from_context()
1767 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
1783 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
2100 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_set_mcif_arb_params()
2147 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_validate_dsc()
2216 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { in dcn20_find_secondary_pipe()
2238 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { in dcn20_find_secondary_pipe()
2269 int split_threshold = dc->res_pool->pipe_count / 2; in dcn20_fast_validate_bw()
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| D | dcn20_hwseq.c | 1167 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_apply_ctx_for_surface()
1194 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_apply_ctx_for_surface()
1232 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_apply_ctx_for_surface()
1251 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_apply_ctx_for_surface()
1323 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_update_bandwidth()
1682 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_reset_back_end_for_pipe()
1686 if (i == dc->res_pool->pipe_count) in dcn20_reset_back_end_for_pipe()
1701 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { in dcn20_reset_hw_ctx_wrap()
2038 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_fpga_init_hw()
2055 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_fpga_init_hw()
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| D | dcn20_dccg.c | 125 switch (dccg_dcn->base.ctx->dc->res_pool->pipe_count) { in dccg2_init()
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| /drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_resource.c | 686 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
773 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce100_validate_bandwidth()
993 pool->base.pipe_count = res_cap.num_timing_generator; in construct()
1000 for (i = 0; i < pool->base.pipe_count; i++) { in construct()
1063 dc->caps.max_planes = pool->base.pipe_count; in construct()
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 856 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
991 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_calculate_wm()
1070 …display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_par… in dcn21_validate_bandwidth()
1279 dcn2_1_ip.max_num_dpp = pool->base.pipe_count; in update_bw_bounding_box()
1460 pool->base.pipe_count = 4; in construct()
1474 pool->base.pipe_count = 4; in construct()
1541 for (i = 0; i < pool->base.pipe_count; i++) { in construct()
1650 dc->caps.max_planes = pool->base.pipe_count; in construct()
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| /drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_resource.c | 552 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
1000 pool->base.pipe_count = res_cap.num_timing_generator; in construct()
1087 for (i = 0; i < pool->base.pipe_count; i++) { in construct()
1163 pool->base.pipe_count = j; in construct()
1178 dc->caps.max_planes = pool->base.pipe_count; in construct()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 107 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
281 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn2_update_clocks()
298 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn2_update_clocks()
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| /drivers/gpu/drm/amd/display/dc/dce112/ |
| D | dce112_resource.c | 705 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
828 dc->res_pool->pipe_count, in dce112_validate_bandwidth()
1160 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in construct()
1245 for (i = 0; i < pool->base.pipe_count; i++) { in construct()
1314 dc->caps.max_planes = pool->base.pipe_count; in construct()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 195 unsigned int pipe_count; member
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| D | dce_calcs.h | 485 int pipe_count,
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| D | rv1_clk_mgr.c | 101 for (i = 0; i < dc->res_pool->pipe_count; i++) { in ramp_up_dispclk_with_dpp()
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dce_calcs.c | 2760 const struct pipe_ctx pipe[], int pipe_count, struct bw_calcs_data *data) in populate_initial_data() argument
2776 for (i = 0; i < pipe_count; i++) { in populate_initial_data()
2886 for (i = 0; i < pipe_count; i++) { in populate_initial_data()
2982 int pipe_count) in all_displays_in_sync() argument
2987 for (i = 0; i < pipe_count; i++) { in all_displays_in_sync()
3018 int pipe_count, in bw_calcs() argument
3026 populate_initial_data(pipe, pipe_count, data); in bw_calcs()
3029 calcs_output->all_displays_in_sync = all_displays_in_sync(pipe, pipe_count); in bw_calcs()
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| D | dcn_calcs.c | 865 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) { in dcn_validate_bandwidth()
1171 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) { in dcn_validate_bandwidth()
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