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Searched refs:pipe_ctx (Results 1 – 25 of 41) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/inc/
Dhw_sequencer.h67 struct pipe_ctx;
87 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
89 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
108 struct pipe_ctx *pipe_ctx);
111 struct pipe_ctx *pipe_ctx,
119 struct pipe_ctx *pipe_ctx,
122 struct pipe_ctx *pipe_ctx,
128 struct pipe_ctx *pipe_ctx);
132 struct pipe_ctx *pipe_ctx);
151 struct pipe_ctx *pipe_ctx);
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Dresource.h94 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx);
100 void resource_build_info_frame(struct pipe_ctx *pipe_ctx);
123 struct pipe_ctx *pipe_ctx);
129 struct pipe_ctx *resource_get_head_pipe_for_stream(
140 struct pipe_ctx *find_idle_secondary_pipe(
143 const struct pipe_ctx *primary_pipe);
170 struct pipe_ctx *pipe_ctx_old,
171 struct pipe_ctx *pipe_ctx);
Ddc_link_dp.h76 bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
77 bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);
78 void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
79 bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
Dcore_types.h78 struct pipe_ctx *pipe_ctx);
80 void core_link_disable_stream(struct pipe_ctx *pipe_ctx);
82 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
113 struct pipe_ctx *(*acquire_idle_pipe_for_layer)(
288 struct pipe_ctx { struct
301 struct pipe_ctx *top_pipe; argument
302 struct pipe_ctx *bottom_pipe; argument
303 struct pipe_ctx *next_odm_pipe; argument
304 struct pipe_ctx *prev_odm_pipe; argument
320 struct pipe_ctx pipe_ctx[MAX_PIPES]; argument
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c183 struct pipe_ctx *pipe_ctx, in dcn20_program_tripleBuffer() argument
186 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { in dcn20_program_tripleBuffer()
187 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( in dcn20_program_tripleBuffer()
188 pipe_ctx->plane_res.hubp, in dcn20_program_tripleBuffer()
476 static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) in dcn20_plane_atomic_disable() argument
478 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn20_plane_atomic_disable()
479 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn20_plane_atomic_disable()
481 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); in dcn20_plane_atomic_disable()
486 if (pipe_ctx->stream_res.gsl_group != 0) in dcn20_plane_atomic_disable()
487 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); in dcn20_plane_atomic_disable()
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Ddcn20_hwseq.h34 struct pipe_ctx *pipe_ctx,
40 struct pipe_ctx *pipe_ctx,
44 struct pipe_ctx *pipe_ctx,
68 bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
71 bool dcn20_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
74 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx);
76 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);
78 void dcn20_disable_stream(struct pipe_ctx *pipe_ctx);
82 struct pipe_ctx *pipe_ctx,
85 void dcn20_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx);
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Ddcn20_resource.c1324 struct pipe_ctx *pipe_ctx, in get_pixel_clock_parameters() argument
1327 const struct dc_stream_state *stream = pipe_ctx->stream; in get_pixel_clock_parameters()
1328 struct pipe_ctx *odm_pipe; in get_pixel_clock_parameters()
1331 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) in get_pixel_clock_parameters()
1336 pixel_clk_params->signal_type = pipe_ctx->stream->signal; in get_pixel_clock_parameters()
1337 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
1367 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) in build_pipe_hw_param() argument
1370 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in build_pipe_hw_param()
1372 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( in build_pipe_hw_param()
1373 pipe_ctx->clock_source, in build_pipe_hw_param()
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/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c271 dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx, in dce110_set_input_transfer_func() argument
274 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; in dce110_set_input_transfer_func()
599 dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx, in dce110_set_output_transfer_func() argument
602 struct transform *xfm = pipe_ctx->plane_res.xfm; in dce110_set_output_transfer_func()
624 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) in dce110_update_info_frame() argument
629 ASSERT(pipe_ctx->stream); in dce110_update_info_frame()
631 if (pipe_ctx->stream_res.stream_enc == NULL) in dce110_update_info_frame()
634 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); in dce110_update_info_frame()
635 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); in dce110_update_info_frame()
641 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dce110_update_info_frame()
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Ddce110_hw_sequencer.h43 void dce110_enable_stream(struct pipe_ctx *pipe_ctx);
45 void dce110_disable_stream(struct pipe_ctx *pipe_ctx);
47 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
50 void dce110_blank_stream(struct pipe_ctx *pipe_ctx);
52 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);
53 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);
55 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);
57 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
Ddce110_resource.c810 const struct pipe_ctx *pipe_ctx, in get_pixel_clock_parameters() argument
813 const struct dc_stream_state *stream = pipe_ctx->stream; in get_pixel_clock_parameters()
821 pixel_clk_params->signal_type = pipe_ctx->stream->signal; in get_pixel_clock_parameters()
822 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
844 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) in dce110_resource_build_pipe_hw_param() argument
846 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in dce110_resource_build_pipe_hw_param()
847 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( in dce110_resource_build_pipe_hw_param()
848 pipe_ctx->clock_source, in dce110_resource_build_pipe_hw_param()
849 &pipe_ctx->stream_res.pix_clk_params, in dce110_resource_build_pipe_hw_param()
850 &pipe_ctx->pll_settings); in dce110_resource_build_pipe_hw_param()
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/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c424 bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx) in dcn10_did_underflow_occur() argument
426 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_did_underflow_occur()
427 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn10_did_underflow_occur()
716 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in false_optc_underflow_wa()
732 struct pipe_ctx *pipe_ctx, in dcn10_enable_stream_timing() argument
736 struct dc_stream_state *stream = pipe_ctx->stream; in dcn10_enable_stream_timing()
744 if (pipe_ctx->top_pipe != NULL) in dcn10_enable_stream_timing()
752 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); in dcn10_enable_stream_timing()
754 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( in dcn10_enable_stream_timing()
755 pipe_ctx->clock_source, in dcn10_enable_stream_timing()
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Ddcn10_hw_sequencer.h40 void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);
46 struct pipe_ctx *pipe_ctx,
56 bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
58 bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
60 bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
64 void set_hdr_multiplier(struct pipe_ctx *pipe_ctx);
67 const struct pipe_ctx *pipe_ctx,
71 struct pipe_ctx *pipe_ctx,
74 bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);
78 struct pipe_ctx *pipe_ctx,
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Ddcn10_resource.c986 const struct pipe_ctx *pipe_ctx, in get_pixel_clock_parameters() argument
989 const struct dc_stream_state *stream = pipe_ctx->stream; in get_pixel_clock_parameters()
992 pixel_clk_params->signal_type = pipe_ctx->stream->signal; in get_pixel_clock_parameters()
993 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
1020 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) in build_pipe_hw_param() argument
1023 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in build_pipe_hw_param()
1025 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( in build_pipe_hw_param()
1026 pipe_ctx->clock_source, in build_pipe_hw_param()
1027 &pipe_ctx->stream_res.pix_clk_params, in build_pipe_hw_param()
1028 &pipe_ctx->pll_settings); in build_pipe_hw_param()
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/drivers/gpu/drm/amd/display/dc/core/
Ddc_resource.c428 const struct pipe_ctx *pipe_with_clk_src, in is_sharable_clk_src()
429 const struct pipe_ctx *pipe) in is_sharable_clk_src()
460 struct pipe_ctx *pipe_ctx) in resource_find_used_clk_src_for_sharing() argument
465 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx)) in resource_find_used_clk_src_for_sharing()
466 return res_ctx->pipe_ctx[i].clock_source; in resource_find_used_clk_src_for_sharing()
547 static void calculate_viewport(struct pipe_ctx *pipe_ctx) in calculate_viewport() argument
549 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; in calculate_viewport()
550 const struct dc_stream_state *stream = pipe_ctx->stream; in calculate_viewport()
551 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; in calculate_viewport()
556 bool pri_split = pipe_ctx->bottom_pipe && in calculate_viewport()
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Ddc_link_hwss.c75 struct pipe_ctx *pipes = in dp_enable_link_phy()
76 link->dc->current_state->res_ctx.pipe_ctx; in dp_enable_link_phy()
272 struct pipe_ctx *pipes = in dp_retrain_link_dp_test()
273 &link->dc->current_state->res_ctx.pipe_ctx[0]; in dp_retrain_link_dp_test()
366 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) in dp_set_dsc_on_rx() argument
368 struct dc *core_dc = pipe_ctx->stream->ctx->dc; in dp_set_dsc_on_rx()
369 struct dc_stream_state *stream = pipe_ctx->stream; in dp_set_dsc_on_rx()
382 void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) in dp_set_dsc_on_stream() argument
384 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in dp_set_dsc_on_stream()
385 struct dc *core_dc = pipe_ctx->stream->ctx->dc; in dp_set_dsc_on_stream()
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Ddc_link.c1430 static void enable_stream_features(struct pipe_ctx *pipe_ctx) in enable_stream_features() argument
1432 struct dc_stream_state *stream = pipe_ctx->stream; in enable_stream_features()
1453 struct pipe_ctx *pipe_ctx) in enable_link_dp() argument
1455 struct dc_stream_state *stream = pipe_ctx->stream; in enable_link_dp()
1478 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { in enable_link_dp()
1485 dp_disable_link_phy(link, pipe_ctx->stream->signal); in enable_link_dp()
1493 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = in enable_link_dp()
1500 pipe_ctx->stream->signal, in enable_link_dp()
1501 pipe_ctx->clock_source->id, in enable_link_dp()
1547 struct pipe_ctx *pipe_ctx) in enable_link_edp() argument
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Ddc_stream.c238 static void delay_cursor_until_vupdate(struct pipe_ctx *pipe_ctx, struct dc *dc) in delay_cursor_until_vupdate() argument
243 struct dc_stream_state *stream = pipe_ctx->stream; in delay_cursor_until_vupdate()
249 vupdate_line = get_vupdate_offset_from_vsync(pipe_ctx); in delay_cursor_until_vupdate()
277 struct pipe_ctx *pipe_to_program = NULL; in dc_stream_set_cursor_attributes()
298 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in dc_stream_set_cursor_attributes() local
300 if (pipe_ctx->stream != stream) in dc_stream_set_cursor_attributes()
304 pipe_to_program = pipe_ctx; in dc_stream_set_cursor_attributes()
306 delay_cursor_until_vupdate(pipe_ctx, core_dc); in dc_stream_set_cursor_attributes()
310 core_dc->hwss.set_cursor_attribute(pipe_ctx); in dc_stream_set_cursor_attributes()
312 core_dc->hwss.set_cursor_sdr_white_level(pipe_ctx); in dc_stream_set_cursor_attributes()
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Ddc.c287 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_adjust_vmin_vmax()
315 struct pipe_ctx *pipe = in dc_stream_get_crtc_position()
316 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_crtc_position()
344 struct pipe_ctx *pipe; in dc_stream_configure_crc()
349 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_configure_crc()
394 struct pipe_ctx *pipe; in dc_stream_get_crc()
398 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_crc()
419 struct pipe_ctx *pipes = NULL; in dc_stream_set_dither_option()
423 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream == in dc_stream_set_dither_option()
425 pipes = &link->dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_set_dither_option()
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Ddc_debug.c321 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in context_timing_trace() local
325 if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx) in context_timing_trace()
328 pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position); in context_timing_trace()
333 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in context_timing_trace() local
335 if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx) in context_timing_trace()
339 pipe_ctx->stream_res.tg->inst, in context_timing_trace()
340 pipe_ctx->stream->timing.h_total, in context_timing_trace()
341 pipe_ctx->stream->timing.v_total, in context_timing_trace()
Ddc_surface.c162 struct pipe_ctx *pipe_ctx = in dc_plane_get_status() local
163 &core_dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_get_status()
165 if (pipe_ctx->plane_state != plane_state) in dc_plane_get_status()
168 pipe_ctx->plane_state->status.is_flip_pending = false; in dc_plane_get_status()
174 struct pipe_ctx *pipe_ctx = in dc_plane_get_status() local
175 &core_dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_get_status()
177 if (pipe_ctx->plane_state != plane_state) in dc_plane_get_status()
180 core_dc->hwss.update_pending_status(pipe_ctx); in dc_plane_get_status()
Ddc_link_dp.c3039 struct pipe_ctx *pipe_ctx, in set_crtc_test_pattern() argument
3043 enum dc_color_depth color_depth = pipe_ctx-> in set_crtc_test_pattern()
3046 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; in set_crtc_test_pattern()
3048 int width = pipe_ctx->stream->timing.h_addressable + in set_crtc_test_pattern()
3049 pipe_ctx->stream->timing.h_border_left + in set_crtc_test_pattern()
3050 pipe_ctx->stream->timing.h_border_right; in set_crtc_test_pattern()
3051 int height = pipe_ctx->stream->timing.v_addressable + in set_crtc_test_pattern()
3052 pipe_ctx->stream->timing.v_border_bottom + in set_crtc_test_pattern()
3053 pipe_ctx->stream->timing.v_border_top; in set_crtc_test_pattern()
3093 pipe_ctx->stream->bit_depth_params = params; in set_crtc_test_pattern()
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/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
Ddce_clk_mgr.c171 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dce_get_max_pixel_clock_for_all_paths() local
173 if (pipe_ctx->stream == NULL) in dce_get_max_pixel_clock_for_all_paths()
177 if (pipe_ctx->top_pipe) in dce_get_max_pixel_clock_for_all_paths()
180 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk) in dce_get_max_pixel_clock_for_all_paths()
181 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; in dce_get_max_pixel_clock_for_all_paths()
186 if (dc_is_dp_signal(pipe_ctx->stream->signal) && in dce_get_max_pixel_clock_for_all_paths()
187 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk) in dce_get_max_pixel_clock_for_all_paths()
188 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; in dce_get_max_pixel_clock_for_all_paths()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
Ddce110_clk_mgr.c132 const struct pipe_ctx *pipe_ctx = NULL; in dce110_fill_display_configs() local
135 if (stream == context->res_ctx.pipe_ctx[k].stream) { in dce110_fill_display_configs()
136 pipe_ctx = &context->res_ctx.pipe_ctx[k]; in dce110_fill_display_configs()
140 ASSERT(pipe_ctx != NULL); in dce110_fill_display_configs()
147 cfg->signal = pipe_ctx->stream->signal; in dce110_fill_display_configs()
148 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; in dce110_fill_display_configs()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clk_mgr.c190 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in get_max_pixel_clock_for_all_paths() local
192 if (pipe_ctx->stream == NULL) in get_max_pixel_clock_for_all_paths()
196 if (pipe_ctx->top_pipe) in get_max_pixel_clock_for_all_paths()
199 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk) in get_max_pixel_clock_for_all_paths()
200 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; in get_max_pixel_clock_for_all_paths()
205 if (dc_is_dp_signal(pipe_ctx->stream->signal) && in get_max_pixel_clock_for_all_paths()
206 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk) in get_max_pixel_clock_for_all_paths()
207 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; in get_max_pixel_clock_for_all_paths()
504 const struct pipe_ctx *pipe_ctx = NULL; in dce110_fill_display_configs() local
507 if (stream == context->res_ctx.pipe_ctx[k].stream) { in dce110_fill_display_configs()
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/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr.c102 struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in ramp_up_dispclk_with_dpp() local
104 if (!pipe_ctx->plane_state) in ramp_up_dispclk_with_dpp()
107 pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control( in ramp_up_dispclk_with_dpp()
108 pipe_ctx->plane_res.dpp, in ramp_up_dispclk_with_dpp()

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