| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_stream.c | 276 struct resource_context *res_ctx; in dc_stream_set_cursor_attributes() local
294 res_ctx = &core_dc->current_state->res_ctx; in dc_stream_set_cursor_attributes()
298 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in dc_stream_set_cursor_attributes()
327 struct resource_context *res_ctx; in dc_stream_set_cursor_position() local
341 res_ctx = &core_dc->current_state->res_ctx; in dc_stream_set_cursor_position()
345 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in dc_stream_set_cursor_position()
489 struct resource_context *res_ctx = in dc_stream_get_vblank_counter() local
490 &core_dc->current_state->res_ctx; in dc_stream_get_vblank_counter()
493 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; in dc_stream_get_vblank_counter()
495 if (res_ctx->pipe_ctx[i].stream != stream) in dc_stream_get_vblank_counter()
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| D | dc_resource.c | 331 struct resource_context *res_ctx, in resource_unreference_clock_source() argument
338 res_ctx->clock_source_ref_count[i]--; in resource_unreference_clock_source()
341 res_ctx->dp_clock_source_ref_count--; in resource_unreference_clock_source()
345 struct resource_context *res_ctx, in resource_reference_clock_source() argument
352 res_ctx->clock_source_ref_count[i]++; in resource_reference_clock_source()
355 res_ctx->dp_clock_source_ref_count++; in resource_reference_clock_source()
359 struct resource_context *res_ctx, in resource_get_clock_source_reference() argument
366 return res_ctx->clock_source_ref_count[i]; in resource_get_clock_source_reference()
369 return res_ctx->dp_clock_source_ref_count; in resource_get_clock_source_reference()
459 struct resource_context *res_ctx, in resource_find_used_clk_src_for_sharing() argument
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| D | dc.c | 287 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_adjust_vmin_vmax()
316 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_crtc_position()
349 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_configure_crc()
398 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_crc()
423 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream == in dc_stream_set_dither_option()
425 pipes = &link->dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_set_dither_option()
460 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { in dc_stream_set_gamut_remap()
461 pipes = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_set_gamut_remap()
477 if (dc->current_state->res_ctx.pipe_ctx[i].stream in dc_stream_program_csc_matrix()
480 pipes = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_program_csc_matrix()
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| D | dc_debug.c | 310 struct resource_context *res_ctx) in context_timing_trace() argument
321 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in context_timing_trace()
333 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in context_timing_trace()
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| D | dc_surface.c | 163 &core_dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_get_status()
175 &core_dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_get_status()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | resource.h | 103 struct resource_context *res_ctx,
108 struct resource_context *res_ctx,
113 struct resource_context *res_ctx,
122 struct resource_context *res_ctx,
126 struct resource_context *res_ctx,
130 struct resource_context *res_ctx,
141 struct resource_context *res_ctx,
177 struct resource_context *res_ctx,
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| D | core_types.h | 106 struct resource_context *res_ctx,
133 struct resource_context *res_ctx,
139 struct resource_context *res_ctx,
386 struct resource_context res_ctx; member
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 1389 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); in dcn20_build_mapped_resource()
1420 static void acquire_dsc(struct resource_context *res_ctx, in acquire_dsc() argument
1432 res_ctx->is_dsc_acquired[pipe_idx] = true; in acquire_dsc()
1438 if (!res_ctx->is_dsc_acquired[i]) { in acquire_dsc()
1440 res_ctx->is_dsc_acquired[i] = true; in acquire_dsc()
1445 static void release_dsc(struct resource_context *res_ctx, in release_dsc() argument
1453 res_ctx->is_dsc_acquired[i] = false; in release_dsc()
1473 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i]; in add_dsc_to_stream_resource()
1478 acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc, i); in add_dsc_to_stream_resource()
1501 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { in remove_dsc_from_stream_resource()
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| D | dcn20_resource.h | 53 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
59 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
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| D | dcn20_hwseq.c | 1168 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn20_apply_ctx_for_surface()
1170 &dc->current_state->res_ctx.pipe_ctx[i]; in dcn20_apply_ctx_for_surface()
1195 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn20_apply_ctx_for_surface()
1197 &dc->current_state->res_ctx.pipe_ctx[i]; in dcn20_apply_ctx_for_surface()
1233 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn20_apply_ctx_for_surface()
1253 dcn20_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); in dcn20_apply_ctx_for_surface()
1324 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn20_update_bandwidth()
1653 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, in dcn20_reset_back_end_for_pipe()
1683 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) in dcn20_reset_back_end_for_pipe()
1703 &dc->current_state->res_ctx.pipe_ctx[i]; in dcn20_reset_hw_ctx_wrap()
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_hw_sequencer.c | 966 if (core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) in dce110_enable_audio_stream()
1275 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. in dce110_enable_stream_timing()
1514 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; in disable_vga_and_power_gate_all_controllers()
1516 &dc->current_state->res_ctx.pipe_ctx[i]); in disable_vga_and_power_gate_all_controllers()
1654 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dce110_set_displaymarks()
1683 struct resource_context *res_ctx, in dce110_set_safe_displaymarks() argument
1695 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) in dce110_set_safe_displaymarks()
1698 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( in dce110_set_safe_displaymarks()
1699 res_ctx->pipe_ctx[i].plane_res.mi, in dce110_set_safe_displaymarks()
1707 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( in dce110_set_safe_displaymarks()
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| D | dce110_resource.c | 872 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); in build_mapped_resource()
905 context->res_ctx.pipe_ctx, in dce110_validate_bandwidth()
1054 struct resource_context *res_ctx = &context->res_ctx; in dce110_acquire_underlay() local
1056 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; in dce110_acquire_underlay()
1058 if (res_ctx->pipe_ctx[underlay_idx].stream) in dce110_acquire_underlay()
1070 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { in dce110_acquire_underlay()
1124 struct resource_context *res_ctx, in dce110_find_first_free_match_stream_enc_for_link() argument
1133 if (!res_ctx->is_stream_enc_acquired[i] && in dce110_find_first_free_match_stream_enc_for_link()
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| D | dce110_resource.h | 49 struct resource_context *res_ctx,
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| D | dce110_hw_sequencer.h | 63 struct resource_context *res_ctx,
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 110 if (!context->res_ctx.pipe_ctx[i].plane_state) in dcn20_update_clocks_update_dpp_dto()
113 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; in dcn20_update_clocks_update_dpp_dto()
114 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
284 if (!context->res_ctx.pipe_ctx[i].plane_state) in dcn2_update_clocks()
287 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; in dcn2_update_clocks()
288 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in dcn2_update_clocks()
301 if (!context->res_ctx.pipe_ctx[i].plane_state) in dcn2_update_clocks()
304 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; in dcn2_update_clocks()
305 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in dcn2_update_clocks()
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| /drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_hw_sequencer.c | 113 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_prepare_bandwidth()
125 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_optimize_bandwidth()
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| D | dce100_resource.h | 50 struct resource_context *res_ctx,
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| D | dce100_resource.c | 753 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); in build_mapped_resource()
774 if (context->res_ctx.pipe_ctx[i].stream) in dce100_validate_bandwidth()
857 struct resource_context *res_ctx, in dce100_find_first_free_match_stream_enc_for_link() argument
866 if (!res_ctx->is_stream_enc_acquired[i] && in dce100_find_first_free_match_stream_enc_for_link()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer.c | 716 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in false_optc_underflow_wa()
843 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, in dcn10_reset_back_end_for_pipe()
864 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) in dcn10_reset_back_end_for_pipe()
886 &dc->current_state->res_ctx.pipe_ctx[i]; in dcn10_hw_wa_force_recovery()
911 &dc->current_state->res_ctx.pipe_ctx[i]; in dcn10_hw_wa_force_recovery()
924 &dc->current_state->res_ctx.pipe_ctx[i]; in dcn10_hw_wa_force_recovery()
934 &dc->current_state->res_ctx.pipe_ctx[i]; in dcn10_hw_wa_force_recovery()
946 &dc->current_state->res_ctx.pipe_ctx[i]; in dcn10_hw_wa_force_recovery()
1090 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn10_init_pipes()
1115 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn10_init_pipes()
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| D | dcn10_resource.h | 46 struct resource_context *res_ctx,
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| D | dcn10_resource.c | 1042 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); in build_mapped_resource()
1093 struct resource_context *res_ctx = &context->res_ctx; in dcn10_acquire_idle_pipe_for_layer() local
1094 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); in dcn10_acquire_idle_pipe_for_layer()
1095 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); in dcn10_acquire_idle_pipe_for_layer()
1216 struct resource_context *res_ctx, in dcn10_find_first_free_match_stream_enc_for_link() argument
1225 if (!res_ctx->is_stream_enc_acquired[i] && in dcn10_find_first_free_match_stream_enc_for_link()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| D | dce110_clk_mgr.c | 135 if (stream == context->res_ctx.pipe_ctx[k].stream) { in dce110_fill_display_configs()
136 pipe_ctx = &context->res_ctx.pipe_ctx[k]; in dce110_fill_display_configs()
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| /drivers/gpu/drm/amd/display/dc/dce112/ |
| D | dce112_resource.c | 771 struct resource_context *res_ctx, in find_matching_pll() argument
800 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); in build_mapped_resource()
827 context->res_ctx.pipe_ctx, in dce112_validate_bandwidth()
892 &context->res_ctx, stream); in resource_map_phy_clock_resources()
903 &context->res_ctx, dc->res_pool, in resource_map_phy_clock_resources()
910 &context->res_ctx, in resource_map_phy_clock_resources()
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| /drivers/gpu/drm/amd/display/include/ |
| D | logger_interface.h | 59 struct resource_context *res_ctx);
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clk_mgr.c | 190 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in get_max_pixel_clock_for_all_paths()
507 if (stream == context->res_ctx.pipe_ctx[k].stream) { in dce110_fill_display_configs()
508 pipe_ctx = &context->res_ctx.pipe_ctx[k]; in dce110_fill_display_configs()
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