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Searched refs:res_pool (Results 1 – 25 of 36) sorted by relevance

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/drivers/bus/fsl-mc/
Dfsl-mc-allocator.c37 struct fsl_mc_resource_pool *res_pool; in fsl_mc_resource_pool_add_device() local
49 res_pool = &mc_bus->resource_pools[pool_type]; in fsl_mc_resource_pool_add_device()
50 if (res_pool->type != pool_type) in fsl_mc_resource_pool_add_device()
52 if (res_pool->mc_bus != mc_bus) in fsl_mc_resource_pool_add_device()
55 mutex_lock(&res_pool->mutex); in fsl_mc_resource_pool_add_device()
57 if (res_pool->max_count < 0) in fsl_mc_resource_pool_add_device()
59 if (res_pool->free_count < 0 || in fsl_mc_resource_pool_add_device()
60 res_pool->free_count > res_pool->max_count) in fsl_mc_resource_pool_add_device()
75 resource->parent_pool = res_pool; in fsl_mc_resource_pool_add_device()
77 list_add_tail(&resource->node, &res_pool->free_list); in fsl_mc_resource_pool_add_device()
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/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c216 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn20_init_blank()
217 opp = dc->res_pool->opps[opp_id_src0]; in dcn20_init_blank()
221 ASSERT(opp_id_src1 < dc->res_pool->res_cap->num_opp); in dcn20_init_blank()
222 bottom_opp = dc->res_pool->opps[opp_id_src1]; in dcn20_init_blank()
481 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); in dcn20_plane_atomic_disable()
630 struct mpc *mpc = dc->res_pool->mpc; in dcn20_program_output_csc()
656 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn20_set_output_transfer_func()
1167 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_apply_ctx_for_surface()
1194 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_apply_ctx_for_surface()
1232 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_apply_ctx_for_surface()
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Ddcn20_resource.c1469 const struct resource_pool *pool = dc->res_pool; in add_dsc_to_stream_resource()
1472 for (i = 0; i < dc->res_pool->pipe_count; i++) { in add_dsc_to_stream_resource()
1505 release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); in remove_dsc_from_stream_resource()
1729 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_writeback_from_context()
1767 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
1783 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
2054 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes); in dcn20_populate_dml_pipes_from_context()
2100 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_set_mcif_arb_params()
2147 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_validate_dsc()
2216 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { in dcn20_find_secondary_pipe()
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Ddcn20_dccg.c125 switch (dccg_dcn->base.ctx->dc->res_pool->pipe_count) { in dccg2_init()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c75 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
105 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_log_hubbub_state()
129 struct resource_pool *pool = dc->res_pool; in dcn10_log_hubp_states()
245 struct resource_pool *pool = dc->res_pool; in dcn10_log_hw_state()
620 struct hubp *hubp = dc->res_pool->hubps[0]; in undo_DEGVIDCN10_253_wa()
640 struct hubp *hubp = dc->res_pool->hubps[0]; in apply_DEGVIDCN10_253_wa()
649 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_DEGVIDCN10_253_wa()
650 if (!dc->res_pool->hubps[i]->power_gated) in apply_DEGVIDCN10_253_wa()
673 if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled) in dcn10_bios_golden_init()
675 dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub); in dcn10_bios_golden_init()
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Ddcn10_hw_sequencer_debug.c80 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubbub_state()
84 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_get_hubbub_state()
112 struct resource_pool *pool = dc->res_pool; in dcn10_get_hubp_states()
118 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubp_states()
190 struct resource_pool *pool = dc->res_pool; in dcn10_get_rq_states()
232 struct resource_pool *pool = dc->res_pool; in dcn10_get_dlg_states()
289 struct resource_pool *pool = dc->res_pool; in dcn10_get_ttu_states()
329 struct resource_pool *pool = dc->res_pool; in dcn10_get_cm_states()
384 struct resource_pool *pool = dc->res_pool; in dcn10_get_mpcc_states()
415 struct resource_pool *pool = dc->res_pool; in dcn10_get_otg_states()
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/drivers/gpu/drm/amd/display/dc/core/
Ddc.c688 dc->res_pool = dc_create_resource_pool(dc, init_params, dc_version); in construct()
689 if (!dc->res_pool) in construct()
692 dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); in construct()
697 if (dc->res_pool->funcs->update_bw_bounding_box) in construct()
698 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); in construct()
752 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_dangling_plane()
795 full_pipe_count = dc->res_pool->pipe_count; in dc_create()
796 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE) in dc_create()
800 dc->res_pool->stream_enc_count); in dc_create()
803 dc->caps.max_audios = dc->res_pool->audio_count; in dc_create()
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Ddc_resource.c130 struct resource_pool *res_pool = NULL; in dc_create_resource_pool() local
134 res_pool = dce80_create_resource_pool( in dc_create_resource_pool()
138 res_pool = dce81_create_resource_pool( in dc_create_resource_pool()
142 res_pool = dce83_create_resource_pool( in dc_create_resource_pool()
146 res_pool = dce100_create_resource_pool( in dc_create_resource_pool()
150 res_pool = dce110_create_resource_pool( in dc_create_resource_pool()
156 res_pool = dce112_create_resource_pool( in dc_create_resource_pool()
161 res_pool = dce120_create_resource_pool( in dc_create_resource_pool()
168 res_pool = dcn10_create_resource_pool(init_data, dc); in dc_create_resource_pool()
175 res_pool = dcn20_create_resource_pool(init_data, dc); in dc_create_resource_pool()
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Ddc_debug.c316 unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index; in context_timing_trace()
320 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { in context_timing_trace()
332 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { in context_timing_trace()
Ddc_surface.c161 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
173 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
Ddc_link_hwss.c73 struct dmcu *dmcu = core_dc->res_pool->dmcu; in dp_enable_link_phy()
78 link->dc->res_pool->dp_clock_source; in dp_enable_link_phy()
178 struct dmcu *dmcu = core_dc->res_pool->dmcu; in dp_disable_link_phy()
Ddc_link.c436 struct audio_support *aud_support = &link->dc->res_pool->audio_support; in link_detect_sink()
747 struct audio_support *aud_support = &link->dc->res_pool->audio_support; in dc_link_detect()
1243 if (link->dc->res_pool->funcs->link_init) in construct()
1244 link->dc->res_pool->funcs->link_init(link); in construct()
1321 link->link_enc = link->dc->res_pool->funcs->link_enc_create( in construct()
2310 struct abm *abm = link->ctx->dc->res_pool->abm; in dc_link_get_backlight_level()
2323 struct abm *abm = core_dc->res_pool->abm; in dc_link_set_backlight_level()
2324 struct dmcu *dmcu = core_dc->res_pool->dmcu; in dc_link_set_backlight_level()
2376 struct abm *abm = core_dc->res_pool->abm; in dc_link_set_abm_disable()
2389 struct dmcu *dmcu = core_dc->res_pool->dmcu; in dc_link_set_psr_enable()
Ddc_stream.c396 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
422 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c201 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in dce110_enable_display_power_gating()
960 if (core_dc->res_pool->pp_smu) in dce110_enable_audio_stream()
961 pp_smu = core_dc->res_pool->pp_smu; in dce110_enable_audio_stream()
1004 if (dc->res_pool->pp_smu) in dce110_disable_audio_stream()
1005 pp_smu = dc->res_pool->pp_smu; in dce110_disable_audio_stream()
1437 for (i = 0; i < dc->res_pool->stream_enc_count; i++) { in power_down_encoders()
1438 dc->res_pool->stream_enc[i]->funcs->dp_blank( in power_down_encoders()
1439 dc->res_pool->stream_enc[i]); in power_down_encoders()
1462 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { in power_down_controllers()
1463 dc->res_pool->timing_generators[i]->funcs->disable_crtc( in power_down_controllers()
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/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c107 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
150 if (dc->res_pool->pp_smu) in request_voltage_and_program_disp_clk()
151 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in request_voltage_and_program_disp_clk()
171 if (dc->res_pool->pp_smu) in request_voltage_and_program_global_dpp_clk()
172 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in request_voltage_and_program_global_dpp_clk()
197 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in dcn2_update_clocks()
211 if (dc->res_pool->pp_smu) in dcn2_update_clocks()
212 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()
281 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn2_update_clocks()
298 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn2_update_clocks()
/drivers/gpu/drm/amd/display/dc/dce100/
Ddce100_hw_sequencer.c113 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_prepare_bandwidth()
125 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_optimize_bandwidth()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
Ddce112_clk_mgr.c76 struct dmcu *dmcu = core_dc->res_pool->dmcu; in dce112_set_clock()
130 struct dmcu *dmcu = core_dc->res_pool->dmcu; in dce112_set_dispclk()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr_vbios_smu.c92 struct dmcu *dmcu = core_dc->res_pool->dmcu; in rv1_vbios_smu_set_dispclk()
Drv1_clk_mgr.c101 for (i = 0; i < dc->res_pool->pipe_count; i++) { in ramp_up_dispclk_with_dpp()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr_vbios_smu.c86 struct dmcu *dmcu = core_dc->res_pool->dmcu; in rn_vbios_smu_set_dispclk()
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c991 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_calculate_wm()
995 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn21_calculate_wm()
1020 if (dc->res_pool->funcs->populate_dml_pipes) in dcn21_calculate_wm()
1021 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, in dcn21_calculate_wm()
1070 …display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_par… in dcn21_validate_bandwidth()
1274 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); in update_bw_bounding_box()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clk_mgr.c254 struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu; in dce_set_clock()
294 struct dmcu *dmcu = core_dc->res_pool->dmcu; in dce112_set_clock()
650 pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz; in dce11_pplib_apply_display_requirements()
/drivers/gpu/drm/amd/display/dc/dce112/
Ddce112_resource.c828 dc->res_pool->pipe_count, in dce112_validate_bandwidth()
900 dc->res_pool->dp_clock_source; in resource_map_phy_clock_resources()
903 &context->res_ctx, dc->res_pool, in resource_map_phy_clock_resources()
911 dc->res_pool, in resource_map_phy_clock_resources()
/drivers/gpu/drm/amd/display/dc/inc/
Dhw_sequencer.h267 struct resource_pool *res_pool,
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c328 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
483 input.clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn_bw_calc_rq_dlg_ttu()
730 const struct resource_pool *pool = dc->res_pool; in dcn_validate_bandwidth()
975 v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format( in dcn_validate_bandwidth()
1494 if (dc->res_pool->pp_smu) in dcn_bw_notify_pplib_of_wm_ranges()
1495 pp = &dc->res_pool->pp_smu->rv_funcs; in dcn_bw_notify_pplib_of_wm_ranges()

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