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Searched refs:top_pipe (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/display/dc/core/
Ddc_resource.c558 bool sec_split = pipe_ctx->top_pipe && in calculate_viewport()
559 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; in calculate_viewport()
662 bool sec_split = pipe_ctx->top_pipe && in calculate_recout()
663 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; in calculate_recout()
1136 && !res_ctx->pipe_ctx[i].top_pipe in resource_get_head_pipe_for_stream()
1204 if (split_pipe->top_pipe && in acquire_first_split_pipe()
1205 split_pipe->top_pipe->plane_state == split_pipe->plane_state) { in acquire_first_split_pipe()
1206 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe; in acquire_first_split_pipe()
1208 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe; in acquire_first_split_pipe()
1210 if (split_pipe->top_pipe->plane_state) in acquire_first_split_pipe()
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Ddc.c874 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe) in program_timing_sync()
1238 if (cur_pipe->top_pipe) in dc_copy_state()
1239 cur_pipe->top_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; in dc_copy_state()
1880 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) { in commit_planes_do_stream_update()
2039 if (!pipe_ctx->top_pipe && in commit_planes_for_stream()
Ddc_link_hwss.c278 !pipes[i].top_pipe && !pipes[i].prev_odm_pipe && in dp_retrain_link_dp_test()
Ddc_link_dp.c3193 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) { in dc_link_dp_set_test_pattern()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c744 if (pipe_ctx->top_pipe != NULL) in dcn10_enable_stream_timing()
854 if (pipe_ctx->top_pipe == NULL) { in dcn10_reset_back_end_for_pipe()
1056 pipe_ctx->top_pipe = NULL; in dcn10_plane_atomic_disable()
1320 if (pipe_ctx_old->top_pipe) in dcn10_reset_hw_ctx_wrap()
1340 bool sec_split = pipe_ctx->top_pipe && in patch_address_for_sbs_tb_stereo()
1341 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
1513 if (pipe->top_pipe) in dcn10_pipe_control_lock()
1916 if (pipe_ctx->top_pipe) { in dcn10_is_rear_mpo_fix_required()
1917 struct pipe_ctx *top = pipe_ctx->top_pipe; in dcn10_is_rear_mpo_fix_required()
1919 while (top->top_pipe) in dcn10_is_rear_mpo_fix_required()
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/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.c1501 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { in remove_dsc_from_stream_resource()
1638 ASSERT(next_odm_pipe->top_pipe == NULL); in dcn20_split_stream_for_odm()
1714 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; in dcn20_split_stream_for_mpc()
1717 secondary_pipe->top_pipe = primary_pipe; in dcn20_split_stream_for_mpc()
1837 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state in dcn20_populate_dml_pipes_from_context()
1839 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx; in dcn20_populate_dml_pipes_from_context()
1966 || (res_ctx->pipe_ctx[i].top_pipe in dcn20_populate_dml_pipes_from_context()
1967 && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln); in dcn20_populate_dml_pipes_from_context()
1995 } else if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) { in dcn20_populate_dml_pipes_from_context()
1997 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width; in dcn20_populate_dml_pipes_from_context()
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Ddcn20_hwseq.c505 pipe_ctx->top_pipe = NULL; in dcn20_plane_atomic_disable()
540 if (pipe_ctx->top_pipe != NULL) in dcn20_enable_stream_timing()
667 if (pipe_ctx->top_pipe == NULL in dcn20_set_output_transfer_func()
1037 if (pipe_ctx->top_pipe == NULL && !pipe_ctx->prev_odm_pipe) { in dcn20_program_all_pipe_in_tree()
1100 if (pipe->top_pipe) in dcn20_pipe_control_lock()
1329 if (pipe_ctx->top_pipe == NULL) { in dcn20_update_bandwidth()
1532 bool sec_split = pipe_ctx->top_pipe && in patch_address_for_sbs_tb_stereo()
1533 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
1669 if (pipe_ctx->top_pipe == NULL) { in dcn20_reset_back_end_for_pipe()
1709 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) in dcn20_reset_hw_ctx_wrap()
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c308 if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) in pipe_ctx_to_e2e_pipe_params()
532 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; in split_stream_across_pipes()
535 secondary_pipe->top_pipe = primary_pipe; in split_stream_across_pipes()
871 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) in dcn_validate_bandwidth()
1178 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) in dcn_validate_bandwidth()
1243 hsplit_pipe->bottom_pipe->top_pipe = pipe; in dcn_validate_bandwidth()
1246 hsplit_pipe->top_pipe = NULL; in dcn_validate_bandwidth()
Ddce_calcs.c2988 if (!pipe[i].stream || pipe[i].top_pipe) in all_displays_in_sync()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c1897 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) in dce110_reset_hw_ctx_wrap()
1979 if (pipe_ctx->top_pipe) in dce110_setup_audio_dto()
2007 if (pipe_ctx->top_pipe) in dce110_setup_audio_dto()
2054 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) in dce110_apply_ctx_to_hw()
2090 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) in dce110_apply_ctx_to_hw()
2595 if (!pipe_ctx->top_pipe && in dce110_apply_ctx_for_surface()
2628 (!pipe_ctx->top_pipe) && in dce110_apply_ctx_for_surface()
2702 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) in dce110_set_cursor_position()
/drivers/gpu/drm/amd/display/dc/inc/
Dcore_types.h301 struct pipe_ctx *top_pipe; member
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
Ddce_clk_mgr.c177 if (pipe_ctx->top_pipe) in dce_get_max_pixel_clock_for_all_paths()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clk_mgr.c196 if (pipe_ctx->top_pipe) in get_max_pixel_clock_for_all_paths()