Searched refs:train_set (Results 1 – 7 of 7) sorted by relevance
/drivers/gpu/drm/i915/display/ |
D | intel_dp_link_training.c | 66 intel_dp->train_set[lane] = v | p; in intel_get_adjust_train() 73 u8 buf[sizeof(intel_dp->train_set) + 1]; in intel_dp_set_link_train() 85 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); in intel_dp_set_link_train() 99 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); in intel_dp_reset_link_train() 112 intel_dp->train_set, intel_dp->lane_count); in intel_dp_update_link_train() 122 if ((intel_dp->train_set[lane] & in intel_dp_link_max_vswing_reached() 215 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in intel_dp_link_training_clock_recovery() 224 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == in intel_dp_link_training_clock_recovery()
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D | intel_dp.c | 3713 u8 train_set = intel_dp->train_set[0]; in vlv_signal_levels() local 3715 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in vlv_signal_levels() 3718 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_signal_levels() 3741 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_signal_levels() 3760 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_signal_levels() 3775 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_signal_levels() 3799 u8 train_set = intel_dp->train_set[0]; in chv_signal_levels() local 3801 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in chv_signal_levels() 3803 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in chv_signal_levels() 3826 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in chv_signal_levels() [all …]
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D | intel_display_types.h | 1180 u8 train_set[4]; member
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D | intel_ddi.c | 2731 u8 train_set = intel_dp->train_set[0]; in intel_ddi_dp_level() local 2732 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | in intel_ddi_dp_level()
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/drivers/gpu/drm/amd/amdgpu/ |
D | atombios_dp.c | 208 u8 train_set[4]) in amdgpu_atombios_dp_get_adjust_train() 240 train_set[lane] = v | p; in amdgpu_atombios_dp_get_adjust_train() 486 u8 train_set[4]; member 498 0, dp_info->train_set[0]); /* sets all lanes at once */ in amdgpu_atombios_dp_update_vs_emph() 502 dp_info->train_set, dp_info->dp_lane_count); in amdgpu_atombios_dp_update_vs_emph() 596 memset(dp_info->train_set, 0, 4); in amdgpu_atombios_dp_link_train_cr() 620 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in amdgpu_atombios_dp_link_train_cr() 628 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in amdgpu_atombios_dp_link_train_cr() 637 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in amdgpu_atombios_dp_link_train_cr() 641 dp_info->train_set); in amdgpu_atombios_dp_link_train_cr() [all …]
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/drivers/gpu/drm/radeon/ |
D | atombios_dp.c | 258 u8 train_set[4]) in dp_get_adjust_train() 290 train_set[lane] = v | p; in dp_get_adjust_train() 548 u8 train_set[4]; member 560 0, dp_info->train_set[0]); /* sets all lanes at once */ in radeon_dp_update_vs_emph() 564 dp_info->train_set, dp_info->dp_lane_count); in radeon_dp_update_vs_emph() 675 memset(dp_info->train_set, 0, 4); in radeon_dp_link_train_cr() 699 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in radeon_dp_link_train_cr() 707 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in radeon_dp_link_train_cr() 716 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in radeon_dp_link_train_cr() 719 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); in radeon_dp_link_train_cr() [all …]
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/drivers/gpu/drm/gma500/ |
D | cdv_intel_dp.c | 270 uint8_t train_set[4]; member 1330 intel_dp->train_set[lane] = v | p; in cdv_intel_get_adjust_train() 1421 intel_dp->train_set, in cdv_intel_dplink_set_level() 1426 intel_dp->train_set[0], intel_dp->lane_count); in cdv_intel_dplink_set_level() 1526 memset(intel_dp->train_set, 0, 4); in cdv_intel_dp_start_link_train() 1538 intel_dp->train_set[0], in cdv_intel_dp_start_link_train() 1545 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); in cdv_intel_dp_start_link_train() 1566 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in cdv_intel_dp_start_link_train() 1572 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in cdv_intel_dp_start_link_train() 1578 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in cdv_intel_dp_start_link_train() [all …]
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