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/Documentation/devicetree/bindings/opp/
Dopp.txt1 Generic OPP (Operating Performance Points) Bindings
2 ----------------------------------------------------
4 Devices work at voltage-current-frequency combinations and some implementations
5 have the liberty of choosing these. These combinations are called Operating
6 Performance Points aka OPPs. This document defines bindings for these OPPs
13 Binding 1: operating-points
16 This binding only supports voltage-frequency pairs.
19 - operating-points: An array of 2-tuples items, and each item consists
20 of frequency and voltage like <freq-kHz vol-uV>.
27 compatible = "arm,cortex-a9";
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Dsun50i-nvmem-cpufreq.txt7 speedbin blown in the efuse combination. The sun50i-cpufreq-nvmem driver
12 --------------------
14 - operating-points-v2: Phandle to the operating-points-v2 table to use.
16 In 'operating-points-v2' table:
17 - compatible: Should be
18 - 'allwinner,sun50i-h6-operating-points'.
19 - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
22 pair. Please refer the for nvmem-cells bindings
27 - opp-microvolt-<name>: Voltage in micro Volts.
29 matching opp-microvolt-<name> property.
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Dqcom-opp.txt3 The bindings are based on top of the operating-points-v2 bindings
10 - compatible: Allow OPPs to express their compatibility. It should be:
11 "operating-points-v2-qcom-level"
16 - qcom,opp-fuse-level: A positive value representing the fuse corner/level
Dqcom-nvmem-cpufreq.txt8 defines the voltage and frequency value based on the msm-id in SMEM
10 The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
13 operating-points-v2 table when it is parsed by the OPP framework.
16 --------------------
18 - operating-points-v2: Phandle to the operating-points-v2 table to use.
20 In 'operating-points-v2' table:
21 - compatible: Should be
22 - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
25 --------------------
27 - power-domains: A phandle pointing to the PM domain specifier which provides
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/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-mediatek.txt5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - #cooling-cells:
30 compatible = "operating-points-v2";
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Dti-cpufreq.txt6 The ti-cpufreq driver can use revision and an efuse value from the SoC to
8 used to determine which OPPs from the operating-points-v2 table get enabled
12 --------------------
14 - operating-points-v2: Phandle to the operating-points-v2 table to use.
16 In 'operating-points-v2' table:
17 - compatible: Should be
18 - 'operating-points-v2-ti-cpu' for am335x, am43xx, and dra7xx/am57xx SoCs
19 - syscon: A phandle pointing to a syscon node representing the control module
23 --------------------
24 For each opp entry in 'operating-points-v2' table:
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Dcpufreq-st.txt12 ----------------------
18 - operating-points : [See: ../power/opp.txt]
21 --------------
26 operating-points = <1500000 0
34 --------------------------------------------
40 - operating-points-v2 : [See ../power/opp.txt]
43 ----------------
47 operating-points-v2 = <&cpu0_opp_table>;
52 compatible = "operating-points-v2";
61 opp-supported-hw = <0x00000004 0xffffffff 0xffffffff>;
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Dimx-cpufreq-dt.txt1 i.MX CPUFreq-DT OPP bindings
6 the opp-supported-hw values for each OPP to check if the OPP is allowed.
9 --------------------
11 For each opp entry in 'operating-points-v2' table:
12 - opp-supported-hw: Two bitmaps indicating:
13 - Supported speed grade mask
14 - Supported market segment mask
21 --------
24 compatible = "operating-points-v2";
25 opp-1000000000 {
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/Documentation/devicetree/bindings/power/
Dqcom,rpmpd.txt7 - compatible: Should be one of the following
8 * qcom,msm8996-rpmpd: RPM Power domain for the msm8996 family of SoC
9 * qcom,msm8998-rpmpd: RPM Power domain for the msm8998 family of SoC
10 * qcom,qcs404-rpmpd: RPM Power domain for the qcs404 family of SoC
11 * qcom,sdm845-rpmhpd: RPMh Power domain for the sdm845 family of SoC
12 - #power-domain-cells: number of cells in Power domain specifier
14 - operating-points-v2: Phandle to the OPP table for the Power domain.
18 Refer to <dt-bindings/power/qcom-rpmpd.h> for the level values for
23 #include <dt-bindings/power/qcom-rpmhpd.h>
25 opp-level values specified in the OPP tables for RPMh power domains
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Dpower_domain.txt12 #power-domain-cells property in the PM domain provider node.
17 - #power-domain-cells : Number of cells in a PM domain specifier;
23 - power-domains : A phandle and PM domain specifier as defined by bindings of
32 - domain-idle-states : A phandle of an idle-state that shall be soaked into a
34 compatible with domain-idle-state specified in [1]. phandles
35 that are not compatible with domain-idle-state will be
37 The domain-idle-state property reflects the idle state of this PM domain and
38 not the idle states of the devices or sub-domains in the PM domain. Devices
39 and sub-domains have their own idle-states independent of the parent
41 considered as capable of being powered-on or powered-off.
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/Documentation/devicetree/bindings/devfreq/
Dexynos-bus.txt4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture
9 is able to measure the current load of sub-blocks.
11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
13 power line. The power line might be shared among one more sub-blocks.
14 So, we can divide into two type of device as the role of each sub-block.
16 - parent bus device
17 - passive bus device
26 VDD_xxx |--- A block (parent)
27 |--- B block (passive)
28 |--- C block (passive)
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Drk3399_dmc.txt4 - compatible: Must be "rockchip,rk3399-dmc".
5 - devfreq-events: Node to get DDR loading, Refer to
7 rockchip-dfi.txt
8 - clocks: Phandles for clock specified in "clock-names" property
9 - clock-names : The name of clock used by the DFI, must be
11 - operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp.txt
13 - center-supply: DMC supply node.
14 - status: Marks the node enabled/disabled.
17 - interrupts: The CPU interrupt number. The interrupt specifier
24 - rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/rk3399-ddr.h,
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/Documentation/devicetree/bindings/display/msm/
Dgmu.txt7 - compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
8 for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
9 Note that you need to list the less specific "qcom,adreno-gmu"
12 - reg: Physical base address and length of the GMU registers.
13 - reg-names: Matching names for the register regions
17 - interrupts: The interrupt signals from the GMU.
18 - interrupt-names: Matching names for the interrupts
21 - clocks: phandles to the device clocks
22 - clock-names: Matching names for the clocks
27 - power-domains: should be:
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Dgpu.txt4 - compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or
5 "amd,imageon-XYZ.W", "amd,imageon"
6 for example: "qcom,adreno-306.0", "qcom,adreno"
9 with the chip-id.
11 - reg: Physical base address and length of the controller's registers.
12 - interrupts: The interrupt signal from the gpu.
13 - clocks: device clocks (if applicable)
14 See ../clocks/clock-bindings.txt for details.
15 - clock-names: the following clocks are required by a3xx, a4xx and a5xx
22 - qcom,adreno-630.2
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/Documentation/devicetree/bindings/gpu/
Darm,mali-bifrost.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-bifrost.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
14 pattern: '^gpu@[a-f0-9]+$'
18 - enum:
19 - amlogic,meson-g12a-mali
20 - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
27 - description: Job interrupt
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Darm,mali-midgard.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-midgard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
14 pattern: '^gpu@[a-f0-9]+$'
17 - items:
18 - enum:
19 - allwinner,sun50i-h6-mali
20 - const: arm,mali-t720
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Darm,mali-utgard.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
11 - Maxime Ripard <maxime.ripard@free-electrons.com>
12 - Heiko Stuebner <heiko@sntech.de>
16 pattern: '^gpu@[a-f0-9]+$'
19 - items:
20 - const: allwinner,sun8i-a23-mali
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/Documentation/admin-guide/
Dcgroup-v2.rst2 Control Group v2
9 conventions of cgroup v2. It describes all userland-visible aspects
12 v1 is available under Documentation/admin-guide/cgroup-v1/.
17 1-1. Terminology
18 1-2. What is cgroup?
20 2-1. Mounting
21 2-2. Organizing Processes and Threads
22 2-2-1. Processes
23 2-2-2. Threads
24 2-3. [Un]populated Notification
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DREADME.rst11 --------------
13 Linux is a clone of the operating system Unix, written from scratch by
14 Linus Torvalds with assistance from a loosely-knit team of hackers across
17 It has all the features you would expect in a modern fully-fledged Unix,
19 loading, shared copy-on-write executables, proper memory management,
22 It is distributed under the GNU General Public License v2 - see the
26 -----------------------------
28 Although originally developed first for 32-bit x86-based PCs (386 or higher),
31 IBM S/390, MIPS, HP PA-RISC, Intel IA-64, DEC VAX, AMD x86-64 Xtensa, and
34 Linux is easily portable to most general-purpose 32- or 64-bit architectures
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/Documentation/virt/uml/
DUserModeLinux-HOWTO.txt130 15.3 Buglets and clean-ups
151 +-----------+-----------+----+
153 +-----------+-----------+----+
155 +----------------------------+
157 +----------------------------+
165 User-Mode Linux as if they were running under a normal kernel, like
170 +----------------+
172 +-----------+----------------+
173 | Process 1 | User-Mode Linux|
174 +----------------------------+
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