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1Qualcomm adreno/snapdragon GPU
2
3Required properties:
4- compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or
5	      "amd,imageon-XYZ.W", "amd,imageon"
6    for example: "qcom,adreno-306.0", "qcom,adreno"
7  Note that you need to list the less specific "qcom,adreno" (since this
8  is what the device is matched on), in addition to the more specific
9  with the chip-id.
10  If "amd,imageon" is used, there should be no top level msm device.
11- reg: Physical base address and length of the controller's registers.
12- interrupts: The interrupt signal from the gpu.
13- clocks: device clocks (if applicable)
14  See ../clocks/clock-bindings.txt for details.
15- clock-names: the following clocks are required by a3xx, a4xx and a5xx
16  cores:
17  * "core"
18  * "iface"
19  * "mem_iface"
20  For GMU attached devices the GPU clocks are not used and are not required. The
21  following devices should not list clocks:
22   - qcom,adreno-630.2
23- iommus: optional phandle to an adreno iommu instance
24- operating-points-v2: optional phandle to the OPP operating points
25- interconnects: optional phandle to an interconnect provider.  See
26  ../interconnect/interconnect.txt for details.
27- qcom,gmu: For GMU attached devices a phandle to the GMU device that will
28  control the power for the GPU. Applicable targets:
29    - qcom,adreno-630.2
30- zap-shader: For a5xx and a6xx devices this node contains a memory-region that
31  points to reserved memory to store the zap shader that can be used to help
32  bring the GPU out of secure mode.
33
34Example 3xx/4xx/a5xx:
35
36/ {
37	...
38
39	gpu: qcom,kgsl-3d0@4300000 {
40		compatible = "qcom,adreno-320.2", "qcom,adreno";
41		reg = <0x04300000 0x20000>;
42		reg-names = "kgsl_3d0_reg_memory";
43		interrupts = <GIC_SPI 80 0>;
44		clock-names =
45		    "core",
46		    "iface",
47		    "mem_iface";
48		clocks =
49		    <&mmcc GFX3D_CLK>,
50		    <&mmcc GFX3D_AHB_CLK>,
51		    <&mmcc MMSS_IMEM_AHB_CLK>;
52	};
53};
54
55Example a6xx (with GMU):
56
57/ {
58	...
59
60	gpu@5000000 {
61		compatible = "qcom,adreno-630.2", "qcom,adreno";
62		#stream-id-cells = <16>;
63
64		reg = <0x5000000 0x40000>, <0x509e000 0x10>;
65		reg-names = "kgsl_3d0_reg_memory", "cx_mem";
66
67		/*
68		 * Look ma, no clocks! The GPU clocks and power are
69		 * controlled entirely by the GMU
70		 */
71
72		interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
73
74		iommus = <&adreno_smmu 0>;
75
76		operating-points-v2 = <&gpu_opp_table>;
77
78		interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
79
80		qcom,gmu = <&gmu>;
81
82		zap-shader {
83			memory-region = <&zap_shader_region>;
84		};
85	};
86};
87