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/Documentation/devicetree/bindings/net/
Dfsl-enetc.txt3 Depending on board design and ENETC port type (internal or
9 - reg : Specifies PCIe Device Number and Function
12 - compatible : Should be "fsl,enetc".
14 1. The ENETC external port is connected to a MDIO configurable phy
18 In this case, the ENETC node should include a "mdio" sub-node
19 that in turn should contain the "ethernet-phy" node describing the
20 external phy. Below properties are required, their bindings
22 Documentation/devicetree/bindings/net/phy.txt.
26 - phy-handle : Phandle to a PHY on the MDIO bus.
29 - phy-connection-type : Defined in ethernet.txt.
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Dfsl-tsec-phy.txt3 The MDIO is a bus to which the PHY devices are connected. For each
5 the definition of the PHY node in booting-without-of.txt for an example
6 of how to define a PHY.
9 - reg : Offset and length of the register set for the device, and optionally
10 the offset and length of the TBIPA register (TBI PHY address
14 - compatible : Should define the compatible device type for the
16 - "fsl,gianfar-tbi"
17 - "fsl,gianfar-mdio"
18 - "fsl,etsec2-tbi"
19 - "fsl,etsec2-mdio"
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Dapm-xgene-enet.txt1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
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Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
16 local-mac-address:
18 - $ref: /schemas/types.yaml#definitions/uint8-array
19 - items:
20 - minItems: 6
25 mac-address:
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Dbrcm,bcmgenet.txt4 - compatible: should contain one of "brcm,genet-v1", "brcm,genet-v2",
5 "brcm,genet-v3", "brcm,genet-v4", "brcm,genet-v5".
6 - reg: address and length of the register set for the device
7 - interrupts and/or interrupts-extended: must be two cells, the first cell
10 optional third interrupt cell for Wake-on-LAN can be specified.
11 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
13 - phy-mode: see ethernet.txt file in the same directory
14 - #address-cells: should be 1
15 - #size-cells: should be 1
18 - clocks: When provided, must be two phandles to the functional clocks nodes
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Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.50a
25 - snps,dwmac-3.610
26 - snps,dwmac-3.70a
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/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
Ducc.txt4 - device_type : should be "network", "hldc", "uart", "transparent"
6 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8 - reg : Offset and length of the register set for the device
9 - interrupts : <a b> where a is the interrupt number and b is a
12 the information in section 2) depending on the type of interrupt
14 - pio-handle : The phandle for the Parallel I/O port configuration.
15 - port-number : for UART drivers, the port number to use, between 0 and 3.
18 CPM UART driver, the port-number is required for the QE UART driver.
19 - soft-uart : for UART drivers, if specified this means the QE UART device
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/Documentation/driver-api/
Ddevice_connection.rst6 ------------
10 could be a PCI device, may need to be able to get a reference to its PHY
15 Device connections are generic descriptions of any type of connection between
22 defined in firmware (not yet supported) or they can be built-in.
25 -----
27 Device connections should exist before device ``->probe`` callback is called for
29 firmware, this is not a problem. It should be considered if the connection
30 descriptions are "built-in", and need to be added separately.
32 The connection description consists of the names of the two devices with the
33 connection, i.e. the endpoints, and unique identifier for the connection which
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/Documentation/networking/device_drivers/intel/
De1000e.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 Linux Driver for Intel(R) Ethernet Network Connection
8 Copyright(c) 2008-2018 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Additional Configurations
16 - Support
48 ---------------------
49 :Valid Range: 0,1,3,4,100-100000
70 that it receives. After determining the type of incoming traffic in the last
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De1000.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 Linux Base Driver for Intel(R) Ethernet Network Connection
8 Copyright(c) 1999 - 2013 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Speed and Duplex Configuration
16 - Additional Configurations
17 - Support
28 website. In the search field, enter your adapter name or type, or use the
50 -------
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/Documentation/networking/
Dphy.rst2 PHY Abstraction Layer
9 to a MAC layer, which communicates with the physical connection through a
10 PHY. The PHY concerns itself with negotiating link parameters with the link
11 partner on the other side of the network connection (typically, an ethernet
17 the PHY management code with the network driver. This has resulted in large
23 accessed are, in fact, busses, the PHY Abstraction Layer treats them as such.
26 #. Increase code-reuse
27 #. Increase overall code-maintainability
30 Basically, this layer is meant to provide an interface to PHY devices which
37 Most network devices are connected to a PHY by means of a management bus.
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/Documentation/devicetree/bindings/net/dsa/
Dsja1105.txt6 - compatible:
8 - "nxp,sja1105e"
9 - "nxp,sja1105t"
10 - "nxp,sja1105p"
11 - "nxp,sja1105q"
12 - "nxp,sja1105r"
13 - "nxp,sja1105s"
18 and the non-SGMII devices, while pin-compatible, are not equal in terms
24 - sja1105,role-mac:
25 - sja1105,role-phy:
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/Documentation/devicetree/bindings/usb/
Dci-hdrc-usb2.txt4 - compatible: should be one of:
5 "fsl,imx23-usb"
6 "fsl,imx27-usb"
7 "fsl,imx28-usb"
8 "fsl,imx6q-usb"
9 "fsl,imx6sl-usb"
10 "fsl,imx6sx-usb"
11 "fsl,imx6ul-usb"
12 "fsl,imx7d-usb"
13 "fsl,imx7ulp-usb"
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/Documentation/driver-api/nfc/
Dnfc-hci.rst5 - Author: Eric Lapuyade, Samuel Ortiz
6 - Contact: eric.lapuyade@intel.com, samuel.ortiz@intel.com
9 -------
12 enables easy writing of HCI-based NFC drivers. The HCI layer runs as an NFC Core
17 ---
30 - one for executing commands : nfc_hci_msg_tx_work(). Only one command
32 - one for dispatching received events and commands : nfc_hci_msg_rx_work().
35 --------------------------
41 In case the chip supports pre-opened gates and pseudo-static pipes, the driver
45 -------------------
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/Documentation/driver-api/usb/
Dtypec.rst3 USB Type-C connector class
7 ------------
9 The typec class is meant for describing the USB Type-C ports in a system to the
14 The platforms are expected to register every USB Type-C port they have with the
15 class. In a normal case the registration will be done by a USB Type-C or PD PHY
18 considers the component registering the USB Type-C ports with the class as "port
26 attributes are described in Documentation/ABI/testing/sysfs-class-typec.
29 --------------------
36 "port0-partner". Full path to the device would be
37 /sys/class/typec/port0/port0-partner/.
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/Documentation/scsi/
Dlibsas.txt2 ---------
8 phy/OOB/link management, the SAS layer is concerned with:
10 * SAS Phy/Port/HA event management (LLDD generates,
22 phy/OOB management, and vendor specific tasks and generates
42 struct sas_phy --------------------
44 phy structure:
55 phy structure.
66 enabled -- must be set (0/1)
67 id -- must be set [0,MAX_PHYS)
68 class, proto, type, role, oob_mode, linkrate -- must be set
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DChangeLog.arcmsr10 ** 1.20.00.00 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error
32 ** working on low quality connection
57 ** 1.implement PCI-Express error recovery function and AER capability
72 ** 1. add arcmsr_enable_eoi_mode() on adapter Type B
73 ** 2. add readl(reg->iop2drv_doorbell_reg) in arcmsr_handle_hbb_isr()
76 ** 1. modify acb->devstate[i][j]
86 ** 2.change the returned value type of arcmsr_build_ccb()
94 ** while Linux XFS over DM-CRYPT.
98 ** 2.fix type B where we should _not_ iounmap() acb->pmu;
100 ** 3.add return -ENOMEM if ioremap() fails
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/Documentation/networking/dsa/
Ddsa.rst22 An Ethernet switch is typically comprised of multiple front-panel ports, and one
27 gateways, or even top-of-the rack switches. This host Ethernet controller will
36 For each front-panel port, DSA will create specialized network devices which are
37 used as controlling and data-flowing endpoints for use by the Linux networking
46 - what port is this frame coming from
47 - what was the reason why this frame got forwarded
48 - how to send CPU originated traffic to specific ports
52 on Port-based VLAN IDs).
57 - the "cpu" port is the Ethernet switch facing side of the management
61 - the "dsa" port(s) are just conduits between two or more switches, and as such
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/Documentation/networking/device_drivers/freescale/dpaa2/
Doverview.rst16 DPAA2 is a hardware architecture designed for high-speeed network
23 DPAA2 hardware resources. The MC provides an object-based abstraction for
28 The MC provides memory-mapped I/O command interfaces (MC portals)
34 +--------------------------------------+
38 +-----------------------------|--------+
44 +------------------------| mc portal |-+
46 | +- - - - - - - - - - - - -V- - -+ |
50 | +- - - - - - - - - - - - - - - -+ |
54 | --------- ------- |
55 | -queues -DPRC |
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