Home
last modified time | relevance | path

Searched refs:DDI_BUF_CTL (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/i915/gvt/
Ddisplay.c232 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; in emulate_monitor_status_change()
233 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
252 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; in emulate_monitor_status_change()
253 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
272 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; in emulate_monitor_status_change()
273 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
290 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; in emulate_monitor_status_change()
Dhandlers.c545 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) in ddi_buf_ctl_mmio_write()
564 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); in fdi_auto_training_started()
2447 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2448 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2449 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2450 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2451 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
/drivers/gpu/drm/i915/display/
Dintel_ddi.c987 i915_reg_t reg = DDI_BUF_CTL(port); in intel_wait_ddi_buf_idle()
1120 I915_WRITE(DDI_BUF_CTL(PORT_E), in hsw_fdi_link_train()
1124 POSTING_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
1167 temp = I915_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
1169 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); in hsw_fdi_link_train()
1170 POSTING_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
1988 tmp = I915_READ(DDI_BUF_CTL(port)); in intel_ddi_get_encoder_pipes()
3326 val = I915_READ(DDI_BUF_CTL(port)); in intel_disable_ddi_buf()
3329 I915_WRITE(DDI_BUF_CTL(port), val); in intel_disable_ddi_buf()
3559 I915_WRITE(DDI_BUF_CTL(port), in intel_enable_ddi_hdmi()
[all …]
Dicl_dsi.c482 tmp = I915_READ(DDI_BUF_CTL(port)); in gen11_dsi_enable_ddi_buffer()
484 I915_WRITE(DDI_BUF_CTL(port), tmp); in gen11_dsi_enable_ddi_buffer()
486 if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) & in gen11_dsi_enable_ddi_buffer()
1149 tmp = I915_READ(DDI_BUF_CTL(port)); in gen11_dsi_disable_port()
1151 I915_WRITE(DDI_BUF_CTL(port), tmp); in gen11_dsi_disable_port()
1153 if (wait_for_us((I915_READ(DDI_BUF_CTL(port)) & in gen11_dsi_disable_port()
Dintel_display.c15270 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) in intel_ddi_crt_present()
15374 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; in intel_setup_outputs()
/drivers/gpu/drm/i915/
Di915_reg.h9471 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) macro