1== Introduction== 2 3LLCC (Last Level Cache Controller) provides last level of cache memory in SOC, 4that can be shared by multiple clients. Clients here are different cores in the 5SOC, the idea is to minimize the local caches at the clients and migrate to 6common pool of memory. Cache memory is divided into partitions called slices 7which are assigned to clients. Clients can query the slice details, activate 8and deactivate them. 9 10Properties: 11- compatible: 12 Usage: required 13 Value type: <string> 14 Definition: must be "qcom,sdm845-llcc" 15 16- reg: 17 Usage: required 18 Value Type: <prop-encoded-array> 19 Definition: The first element specifies the llcc base start address and 20 the size of the register region. The second element specifies 21 the llcc broadcast base address and size of the register region. 22 23- reg-names: 24 Usage: required 25 Value Type: <stringlist> 26 Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base". 27 28- interrupts: 29 Usage: required 30 Definition: The interrupt is associated with the llcc edac device. 31 It's used for llcc cache single and double bit error detection 32 and reporting. 33 34Example: 35 36 cache-controller@1100000 { 37 compatible = "qcom,sdm845-llcc"; 38 reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; 39 reg-names = "llcc_base", "llcc_broadcast_base"; 40 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 41 }; 42