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1Renesas R-Car LVDS Encoder
2==========================
3
4These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
5Gen2, R-Car Gen3 and RZ/G SoCs.
6
7Required properties:
8
9- compatible : Shall contain one of
10  - "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
11  - "renesas,r8a7744-lvds" for R8A7744 (RZ/G1N) compatible LVDS encoders
12  - "renesas,r8a774a1-lvds" for R8A774A1 (RZ/G2M) compatible LVDS encoders
13  - "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders
14  - "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
15  - "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders
16  - "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders
17  - "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders
18  - "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders
19  - "renesas,r8a77965-lvds" for R8A77965 (R-Car M3-N) compatible LVDS encoders
20  - "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders
21  - "renesas,r8a77980-lvds" for R8A77980 (R-Car V3H) compatible LVDS encoders
22  - "renesas,r8a77990-lvds" for R8A77990 (R-Car E3) compatible LVDS encoders
23  - "renesas,r8a77995-lvds" for R8A77995 (R-Car D3) compatible LVDS encoders
24
25- reg: Base address and length for the memory-mapped registers
26- clocks: A list of phandles + clock-specifier pairs, one for each entry in
27  the clock-names property.
28- clock-names: Name of the clocks. This property is model-dependent.
29  - The functional clock, which mandatory for all models, shall be listed
30    first, and shall be named "fck".
31  - On R8A77990, R8A77995 and R8A774C0, the LVDS encoder can use the EXTAL or
32    DU_DOTCLKINx clocks. Those clocks are optional. When supplied they must be
33    named "extal" and "dclkin.x" respectively, with "x" being the DU_DOTCLKIN
34    numerical index.
35  - When the clocks property only contains the functional clock, the
36    clock-names property may be omitted.
37- resets: A phandle + reset specifier for the module reset
38
39Required nodes:
40
41The LVDS encoder has two video ports. Their connections are modelled using the
42OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
43
44- Video port 0 corresponds to the parallel RGB input
45- Video port 1 corresponds to the LVDS output
46
47Each port shall have a single endpoint.
48
49Optional properties:
50
51- renesas,companion : phandle to the companion LVDS encoder. This property is
52  mandatory for the first LVDS encoder on D3 and E3 SoCs, and shall point to
53  the second encoder to be used as a companion in dual-link mode. It shall not
54  be set for any other LVDS encoder.
55
56
57Example:
58
59	lvds0: lvds@feb90000 {
60		compatible = "renesas,r8a77990-lvds";
61		reg = <0 0xfeb90000 0 0x20>;
62		clocks = <&cpg CPG_MOD 727>;
63		power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
64		resets = <&cpg 727>;
65
66		renesas,companion = <&lvds1>;
67
68		ports {
69			#address-cells = <1>;
70			#size-cells = <0>;
71
72			port@0 {
73				reg = <0>;
74				lvds0_in: endpoint {
75					remote-endpoint = <&du_out_lvds0>;
76				};
77			};
78			port@1 {
79				reg = <1>;
80				lvds0_out: endpoint {
81				};
82			};
83		};
84	};
85