1* Freescale Smart Direct Memory Access (SDMA) Controller for i.MX 2 3Required properties: 4- compatible : Should be one of 5 "fsl,imx25-sdma" 6 "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma" 7 "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma" 8 "fsl,imx51-sdma" 9 "fsl,imx53-sdma" 10 "fsl,imx6q-sdma" 11 "fsl,imx7d-sdma" 12 "fsl,imx8mq-sdma" 13 The -to variants should be preferred since they allow to determine the 14 correct ROM script addresses needed for the driver to work without additional 15 firmware. 16- reg : Should contain SDMA registers location and length 17- interrupts : Should contain SDMA interrupt 18- #dma-cells : Must be <3>. 19 The first cell specifies the DMA request/event ID. See details below 20 about the second and third cell. 21- fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM 22 scripts firmware 23 24The second cell of dma phandle specifies the peripheral type of DMA transfer. 25The full ID of peripheral types can be found below. 26 27 ID transfer type 28 --------------------- 29 0 MCU domain SSI 30 1 Shared SSI 31 2 MMC 32 3 SDHC 33 4 MCU domain UART 34 5 Shared UART 35 6 FIRI 36 7 MCU domain CSPI 37 8 Shared CSPI 38 9 SIM 39 10 ATA 40 11 CCM 41 12 External peripheral 42 13 Memory Stick Host Controller 43 14 Shared Memory Stick Host Controller 44 15 DSP 45 16 Memory 46 17 FIFO type Memory 47 18 SPDIF 48 19 IPU Memory 49 20 ASRC 50 21 ESAI 51 22 SSI Dual FIFO (needs firmware ver >= 2) 52 23 Shared ASRC 53 24 SAI 54 55The third cell specifies the transfer priority as below. 56 57 ID transfer priority 58 ------------------------- 59 0 High 60 1 Medium 61 2 Low 62 63Optional properties: 64 65- gpr : The phandle to the General Purpose Register (GPR) node. 66- fsl,sdma-event-remap : Register bits of sdma event remap, the format is 67 <reg shift val>. 68 reg is the GPR register offset. 69 shift is the bit position inside the GPR register. 70 val is the value of the bit (0 or 1). 71 72Examples: 73 74sdma@83fb0000 { 75 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 76 reg = <0x83fb0000 0x4000>; 77 interrupts = <6>; 78 #dma-cells = <3>; 79 fsl,sdma-ram-script-name = "sdma-imx51.bin"; 80}; 81 82DMA clients connected to the i.MX SDMA controller must use the format 83described in the dma.txt file. 84 85Examples: 86 87ssi2: ssi@70014000 { 88 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 89 reg = <0x70014000 0x4000>; 90 interrupts = <30>; 91 clocks = <&clks 49>; 92 dmas = <&sdma 24 1 0>, 93 <&sdma 25 1 0>; 94 dma-names = "rx", "tx"; 95 fsl,fifo-depth = <15>; 96}; 97 98Using the fsl,sdma-event-remap property: 99 100If we want to use SDMA on the SAI1 port on a MX6SX: 101 102&sdma { 103 gpr = <&gpr>; 104 /* SDMA events remap for SAI1_RX and SAI1_TX */ 105 fsl,sdma-event-remap = <0 15 1>, <0 16 1>; 106}; 107 108The fsl,sdma-event-remap property in this case has two values: 109- <0 15 1> means that the offset is 0, so GPR0 is the register of the 110SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX. 111Setting bit 15 to 1 selects SAI1_RX. 112- <0 16 1> means that the offset is 0, so GPR0 is the register of the 113SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX. 114Setting bit 16 to 1 selects SAI1_TX. 115