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1* Renesas R-Car generation 2 USB PHY
2
3This file provides information on what the device node for the R-Car generation
42 USB PHY contains.
5
6Required properties:
7- compatible: "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC.
8	      "renesas,usb-phy-r8a7744" if the device is a part of R8A7744 SoC.
9	      "renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC.
10	      "renesas,usb-phy-r8a77470" if the device is a part of R8A77470 SoC.
11	      "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
12	      "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
13	      "renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC.
14	      "renesas,rcar-gen2-usb-phy" for a generic R-Car Gen2 or
15					  RZ/G1 compatible device.
16
17	      When compatible with the generic version, nodes must list the
18	      SoC-specific version corresponding to the platform first
19	      followed by the generic version.
20
21- reg: offset and length of the register block.
22- #address-cells: number of address cells for the USB channel subnodes, must
23		  be <1>.
24- #size-cells: number of size cells for the USB channel subnodes, must be <0>.
25- clocks: clock phandle and specifier pair.
26- clock-names: string, clock input name, must be "usbhs".
27
28The USB PHY device tree node should have the subnodes corresponding to the USB
29channels. These subnodes must contain the following properties:
30- reg: the USB controller selector; see the table below for the values.
31- #phy-cells: see phy-bindings.txt in the same directory, must be <1>.
32
33The phandle's argument in the PHY specifier is the USB controller selector for
34the USB channel other than r8a77470 SoC; see the selector meanings below:
35
36+-----------+---------------+---------------+
37|\ Selector |               |               |
38+ --------- +       0       |       1       |
39| Channel  \|               |               |
40+-----------+---------------+---------------+
41| 0         | PCI EHCI/OHCI | HS-USB        |
42| 2         | PCI EHCI/OHCI | xHCI          |
43+-----------+---------------+---------------+
44
45For r8a77470 SoC;see the selector meaning below:
46
47+-----------+---------------+---------------+
48|\ Selector |               |               |
49+ --------- +       0       |       1       |
50| Channel  \|               |               |
51+-----------+---------------+---------------+
52| 0         | EHCI/OHCI     | HS-USB        |
53+-----------+---------------+---------------+
54
55Example (Lager board):
56
57	usb-phy@e6590100 {
58		compatible = "renesas,usb-phy-r8a7790", "renesas,rcar-gen2-usb-phy";
59		reg = <0 0xe6590100 0 0x100>;
60		#address-cells = <1>;
61		#size-cells = <0>;
62		clocks = <&cpg CPG_MOD 704>;
63		clock-names = "usbhs";
64		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
65		resets = <&cpg 704>;
66
67		usb0: usb-channel@0 {
68			reg = <0>;
69			#phy-cells = <1>;
70		};
71		usb2: usb-channel@2 {
72			reg = <2>;
73			#phy-cells = <1>;
74		};
75	};
76
77Example (iWave RZ/G1C sbc):
78
79	usbphy0: usb-phy0@e6590100 {
80		compatible = "renesas,usb-phy-r8a77470",
81			     "renesas,rcar-gen2-usb-phy";
82		reg = <0 0xe6590100 0 0x100>;
83		#address-cells = <1>;
84		#size-cells = <0>;
85		clocks = <&cpg CPG_MOD 704>;
86		clock-names = "usbhs";
87		power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
88		resets = <&cpg 704>;
89
90		usb0: usb-channel@0 {
91			reg = <0>;
92			#phy-cells = <1>;
93		};
94	};
95
96	usbphy1: usb-phy@e6598100 {
97		compatible = "renesas,usb-phy-r8a77470",
98			     "renesas,rcar-gen2-usb-phy";
99		reg = <0 0xe6598100 0 0x100>;
100		#address-cells = <1>;
101		#size-cells = <0>;
102		clocks = <&cpg CPG_MOD 706>;
103		clock-names = "usbhs";
104		power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
105		resets = <&cpg 706>;
106
107		usb1: usb-channel@0 {
108			reg = <0>;
109			#phy-cells = <1>;
110		};
111	};
112